Customizing the Board
8-7
n
Dual-Stage Watchdog
The dual-stage watchdog consists of a second watchdog in cascade with the first one: in
the event the first watchdog failed to toggle, the second stage is set to grant the system an
additional 1.6s delay prior to the system reset.
Before the second stage watchdog resets the system, the first watchdog output can be tied
to the ISA’s IOCHK line to generate an NMI to the CPU, while the two watchdog values
are stored. These values may be used to determine the cause of the system’s reset.
CAUTION
The user program must provide the first access to address 190h (or
290h or 390h depending on the I/O address selected in BIOS setup), and
must also include the refresh routine.
n
Watchdog Flags
The watchdog status can be read from two bits (5 and 6) of the system register located
at the address 191h, 291h or 391h (depending on the I/O address selected in CMOS
setup).
The register bits are specified as follows:
Register
Bit #
Function
Software Programming
190h
0-7
Reserved
Reserved
191h
0-4, 6
Reserved
Reserved
5
Watchdog reset history status
Read: 1 = Last system reset caused
by the watchdog timeout
7
Push button reset history status
Read: 1 = Last system reset caused
by the push button reset switch
192h
0
Clear history status (watchdog
and push button)
Read/Write:
0 = Clear,
1 = Normal
1-7
Reserved
Reserved
193h
0-7
Reserved
Reserved
1
May be reprogrammed in the AWARD Chipset Features Setup to addresses 290h-293h or 390h-393h
Summary of Contents for TEK-CPCI 1003
Page 15: ...TEK CPCI 1003 Technical Reference Manual 5 4 5 1 CONNECTOR LOCATION...
Page 22: ...FEATURE DESCRIPTION 7 ONBOARD FEATURES...
Page 51: ...TEK CPCI 1003 Technical Reference Manual 9 2 JUMPER LOCATION...
Page 52: ...Setting Jumpers 9 3 JUMPER SETTINGS Table 1...
Page 53: ...TEK CPCI 1003 Technical Reference Manual 9 4 JUMPER SETTINGS TABLE 2...
Page 67: ...SOFTWARE SETUPS 12 AWARD SETUP PROGRAM 13 UPDATING THE BIOS WITH UPGBIOS 14 VT100 MODE...
Page 95: ...C 1 C BOARD DIAGRAMS C 1 ASSEMBLY TOP DIAGRAM...
