xiv
TABLE OF FIGURES
PAGE
Figure 1-1.
The Pentium
®
Pro Processor Integrating the CPU, L2 Cache,
APIC and Bus Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Figure 1-2.
Pentium
®
Pro Processor System Interface Block Diagram. . . . . . . . . . . . . . . . 1-5
Figure 2-1.
Three Engines Communicating Using an Instruction Pool . . . . . . . . . . . . . . . . 2-1
Figure 2-2.
A Typical Code Fragment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Figure 2-3.
The Three Core Engines Interface with Memory via Unified Caches . . . . . . . . 2-3
Figure 2-4.
Inside the Fetch/Decode Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Figure 2-5.
Inside the Dispatch/Execute Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Figure 2-6.
Inside the Retire Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Figure 2-7.
Inside the Bus Interface Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Figure 3-1.
Latched Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Figure 3-2.
Pentium
®
Pro Processor Bus Transaction Phases . . . . . . . . . . . . . . . . . . . . . . 3-5
Figure 4-1.
BR[3:0]# Physical Interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Figure 4-2.
Symmetric Arbitration of a Single Agent After RESET# . . . . . . . . . . . . . . . . . . 4-6
Figure 4-3.
Signal Deassertion After Bus Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
Figure 4-4.
Delay of Transaction Generation After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
Figure 4-5.
Symmetric Bus Arbitration with no LOCK# . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
Figure 4-6.
Symmetric Arbitration with no Transaction Generation . . . . . . . . . . . . . . . . . 4-11
Figure 4-7.
Bus Exchange Among Symmetric and Priority Agent with no LOCK# . . . . . . 4-12
Figure 4-8.
Symmetric and Priority Bus Exchange During LOCK# . . . . . . . . . . . . . . . . . . 4-13
Figure 4-9.
BNR# Sampling After RESET#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
Figure 4-10.
BNR# Sampling After ADS# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
Figure 4-11.
Request Generation Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
Figure 4-12.
Four-Clock Snoop Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22
Figure 4-13.
Snoop Phase Stall Due to a Slower Agent . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23
Figure 4-14.
RS[2:0]# Activation with no TRDY# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27
Figure 4-15.
RS[2:0]# Activation with Request Initiated TRDY# . . . . . . . . . . . . . . . . . . . . . 4-28
Figure 4-16.
RS[2:0]# Activation with Snoop Initiated TRDY# . . . . . . . . . . . . . . . . . . . . . . 4-29
Figure 4-17.
RS[2:0]# Activation After Two TRDY# Assertions . . . . . . . . . . . . . . . . . . . . . 4-30
Figure 4-18.
Request Initiated Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34
Figure 4-19.
Response Initiated Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35
Figure 4-20.
Snoop Initiated Data Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-36
Figure 4-21.
Full Speed Read Partial Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-37
Figure 4-22.
Relaxed DBSY# Deassertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38
Figure 4-23.
Full Speed Read Line Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39
Figure 4-24.
Full Speed Write Partial Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-40
Figure 4-25.
Full Speed Write Line Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-41
Figure 5-1.
Bus Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Figure 5-2.
Response Responsibility Pickup Effect on an Outstanding Invalidation
Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
Figure 5-3.
Deferred Response Followed by a Deferred Reply to a Read Operation. . . . 5-18
Figure 8-1.
BERR# Protocol Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
Figure 8-2.
BINIT# Protocol Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10
Figure 8-3.
Pentium
®
Pro Processor Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11
Figure 9-1.
Hardware Configuration Signal Sampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
Figure 9-2.
BR[3:0]# Physical Interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
Figure 10-1.
Simplified Block Diagram of Pentium
®
Pro Processor TAP logic . . . . . . . . . . 10-1
Figure 10-2.
TAP Controller Finite State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
Figure 10-3.
Pentium
®
Pro Processor TAP instruction Register . . . . . . . . . . . . . . . . . . . . . 10-4
Summary of Contents for Pentium Pro Family
Page 17: ...1 Component Introduction ...
Page 26: ...2 Pentium Pro Processor Architecture Overview ...
Page 27: ......
Page 36: ...3 Bus Overview ...
Page 62: ...4 Bus Protocol ...
Page 105: ...5 Bus Transactions and Operations ...
Page 126: ...6 Range Registers ...
Page 131: ...7 Cache Protocol ...
Page 135: ...8 Data Integrity ...
Page 148: ...9 Configuration ...
Page 161: ...10 Pentium Pro Processor Test Access Port TAP ...
Page 172: ...11 Electrical Specifications ...
Page 201: ...12 GTL Interface Specification ...
Page 229: ...13 3 3V Tolerant Signal Quality Specifications ...
Page 233: ...14 Thermal Specifications ...
Page 239: ...15 Mechanical Specifications ...
Page 241: ...15 2 MECHANICAL SPECIFICATIONS s Figure 15 1 Package Dimensions Bottom View ...
Page 252: ...16 Tools ...
Page 260: ...16 8 TOOLS Figure 16 4 Generic MP System Layout for Debug Port Connection ...
Page 264: ...17 OverDrive Processor Socket Specification ...
Page 290: ...A Signals Reference ...
Page 320: ...Index ...
Page 328: ......