A-14
SIGNALS REFERENCE
A.1.29. FRCERR(I/O)
The FRCERR signal is the Error group Functional-redundancy-check Error signal. If two Pen-
tium Pro processors are configured in an FRC pair, as a single “logical” processor, then the
checker processor asserts FRCERR if it detects a mismatch between its internally sampled out-
puts and the master processor’s outputs. The checker’s FRCERR output pin is connected to the
master’s FRCERR input pin.
For point-to-point connections, the checker always compares against the master’s outputs. For
bussed single-driver signals, the checker compares against the signal when the master is the only
allowed driver. For bussed multiple-driver Wire-OR signals, the checker compares against the
signal only if the master is expected to drive the signal low.
FRCERR is also toggled during the Pentium Pro processor’s reset action. A Pentium Pro pro-
cessor asserts FRCERR for approximately 1 second after RESET’s active-to-inactive transition
if it executes its built-in self-test (BIST). When BIST execution completes, the Pentium Pro pro-
cessor de-asserts FRCERR if BIST completed successfully and continues to assert FRCERR if
BIST fails. If the Pentium Pro processor does not execute the BIST action, then it keeps
FRCERR asserted for approximately 20 clocks and then de-asserts it.
Chapter 9, Configuration describes how a Pentium Pro processor can be configured as a master
or a checker.
A.1.30. HIT# (I/O), HITM#(I/O)
The HIT# and HITM# signals are Snoop-hit and Hit-modified signals. They are snoop results
asserted by any Pentium Pro processor bus agent in the Snoop Phase.
Any bus agent can assert both HIT# and HITM# together for one clock in the Snoop Phase to
indicate that it requires a snoop stall. When a stall condition is sampled, all bus agents extend
the Snoop Phase by two clocks. The stall can be continued by reasserting HIT# and HITM# to-
gether every other clock for one clock.
A caching agent must assert HITM# for one clock in the Snoop Phase if the transaction hits a
Modified line, and the snooping agent must perform an implicit writeback to update main mem-
ory. The snooping agent with the Modified line makes a transition to Shared state if the original
transaction is Read Line or Read Partial, otherwise it transitions to Invalid state. A Deferred Re-
ply transaction may have HITM# asserted to indicate the return of unexpected data.
A snooping agent must assert HIT# for one clock during the Snoop Phase if the line does not hit
a Modified line in its writeback cache and if at the end of the transaction it plans to keep the line
in Shared state. Multiple caching agents can assert HIT# in the same Snoop Phase. If the request-
ing agent observes HIT# active during the Snoop Phase it can not cache the line in Exclusive or
Modified state.
On observing a snoop stall, the agents asserting HIT# and HITM# independently reassert the
signal after one inactive clock so that the correct snoop result is available, in case the Snoop
Phase terminates after the two clock extension.
Summary of Contents for Pentium Pro Family
Page 17: ...1 Component Introduction ...
Page 26: ...2 Pentium Pro Processor Architecture Overview ...
Page 27: ......
Page 36: ...3 Bus Overview ...
Page 62: ...4 Bus Protocol ...
Page 105: ...5 Bus Transactions and Operations ...
Page 126: ...6 Range Registers ...
Page 131: ...7 Cache Protocol ...
Page 135: ...8 Data Integrity ...
Page 148: ...9 Configuration ...
Page 161: ...10 Pentium Pro Processor Test Access Port TAP ...
Page 172: ...11 Electrical Specifications ...
Page 201: ...12 GTL Interface Specification ...
Page 229: ...13 3 3V Tolerant Signal Quality Specifications ...
Page 233: ...14 Thermal Specifications ...
Page 239: ...15 Mechanical Specifications ...
Page 241: ...15 2 MECHANICAL SPECIFICATIONS s Figure 15 1 Package Dimensions Bottom View ...
Page 252: ...16 Tools ...
Page 260: ...16 8 TOOLS Figure 16 4 Generic MP System Layout for Debug Port Connection ...
Page 264: ...17 OverDrive Processor Socket Specification ...
Page 290: ...A Signals Reference ...
Page 320: ...Index ...
Page 328: ......