Rev. 3.0, 03/01, page 42 of 390
5.2
CPU Interface Signal Description
5.2.1
System Bus Interface Signals
In system bus interface, the configuration of BSC in SH-4/SH-3 needs to be programmed properly.
The followings list the bus configuration requirements.
1. Area: Area 4
2. Bus width: Longword (32 bits) size and little endian access.
3. Idle state: No idle cycles
4. Wait state: 3 wait states
Signal Name
I/O Type
Description
CKIO
I
CKIO: SH3/SH4 system clock IO. This clock is used as the master clock for
the internal logic of the CPU Interface
RESET#
I
RESET#: System reset signal.
CS4#
I
CS4#: System Chip select 4 signal.
RDY/WAIT#
O
System Wait: This signal is controlled by the CPU Interface to insert the wait
state in CPU cycle. The inserted wait cycles are depended on peripheral
*
WAIT#.
ADDR[20:1]
I
Address Bus [20:1]: These are the address input signals to the CPU
Interface. The CPU Interface address decoder uses these signals to decode
the module select(
*
MS#) signal of all peripheral modules in IPC.
ADDR24
I
Address bus 24: This signal is address bus number 24 driven by the CPU.
ADDR25
I
Address bus 25: This signal is address bus number 25 driven by the CPU.
IDATA[31:0]
I
Input Data Bus [31:0]: These are the bit[31:0] of data bus driven by
SH3/SH4.(write data).
ODATA[31:0]
O
Output Data Bus [31:0]: These are the bit[31:0] of data bus to be read by the
CPU.(read data).
RDWR#
I
Read/Write Command: System read/write indicator driven by the CPU.
RD#
I
Read Command: When active along with CS4#, a valid data will be put onto
the ODATA[15:0] for the Host CPU to read. This signal is driven by the CPU.
WE0#
I
Write byte 0 Command: When active along with CS4#, a valid data will be
passed from the Host CPU to MIDATA[7:0]. This signal is driven by the CPU.
WE1#
I
Write byte 1 Command: When active along with CS4#, a valid data will be
passed from the Host CPU to MIDATA[15:8]. This signal is driven by the CPU.
WE2#
I
Write byte 2 Command: When active along with CS4#, a valid data will be
passed from the Host CPU to MIDATA[23:16]. This signal is driven by the
CPU.
WE3#
I
Write byte 3 Command: When active along with CS4#, a valid data will be
passed from the Host CPU to MIDATA[31:24]. This signal is driven by the
CPU.
Notes: 1.
*
stands for peripheral module name.
2. # means that a signal is active low.
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