XRT86VL38
PRELIMINARY
xr
OCTAL T1/E1/J1 FRAMER/LIU COMBO
REV. P1.0.6
55
3.1.2
The Intel-Asynchronous Write Cycle
If the Microprocessor Interface has been configured to operate in the Intel-Asynchronous Mode, then the
Microprocessor should do all of the following to perform a write cycle:
1.
Place the address of the "target" register or buffer location on the Address Bus input pins, A[14:0].
While the microprocessor is placing the address value on the Address Bus, the Address Decoding circuitry
(within the user's system) should assert the CS* (Chip Select) input pin of the XRT86VL38 device, by toggling
it "low". This action enables further communication between the microprocessor and the XRT86VL38
Microprocessor Interface.
2.
Toggle the ALE/AS* (Address Latch Enable) input pin "high". This step enables the "Address Bus" input
drivers, within the Microprocessor Interface block of the XRT86VL38 device.
3.
After allowing the data on the Address Bus pins to settle (by waiting the appropriate "Address Setup" time);
the microprocessor should toggle the ALE/AS* input pin "low". This step causes the XRT86VL38 device to
"latch" the contents of the "Address Bus" into its internal circuitry. At this point, the address of the register
or buffer locations (within the XRT86VL38 device) has now been selected.
4.
Next, the microprocessor should then place the byte that it intends to write into the "target" register into the
XRT86VL38 device, on the bi-directional data bus pins (D[7:0]).
5.
Afterwards, the microprocessor should then indicate that this current bus cycle is a "Write" Operation; by
toggling the WR*/R/W (Write Strobe) input pin "low". This action also enables the "bi-directional" data bus
input drivers of the XRT86VL38 device. At this point, the "bi-directional" data bus input drivers will proceed
to drive the contents (currently residing on the Bi-Directional Data bus into the register) that corresponds
with the "latched address".
6.
Immediately after the microprocessor toggles the "Write Strobe" (WR*/R/W*) signal "low", the XRT86VL38
device will continue to drive the "RDY*/DTACK* output pin "high". The XRT86VL38 device does this in
order to inform the microprocessor that the data (to be written into the "target" address location (within the
XRT86VL38 device) is "NOT READY" to be latched into the microprocessor. In this case, the microproces-
F
IGURE
3. I
NTEL
µP I
NTERFACE
S
IGNALS
D
URING
R
EAD
O
PERATIONS
R D */D S *
R D Y */D T AC K *
AL E /AS
A[14:0]
C S *
D [7:0]
N ot V alid
V alid
Ad dre ss of Targe t R eg ister
W R */R /W *
M icro p ro c es so r In terfa c e la tc he s c o n ten ts o n
A [1 4 :0] u p o n fallin g e d g e o f AL E
R e ad O p e ra tion b eg in s
H e re
R D Y* to g g le s “low ” to in d ic ate
Th a t va lid d a ta c a n b e re a d fro m
D [7 :0]
R e ad O p e ra tion is
Te rm in a te d H ere
R D Y* to g g le “h ig h ” afte r
C o m p letio n o f R e a d
O p e ra tio n
M ic ro p ro c es so r p lac e s “targ et”
Ad d re ss va lu e o n A[1 4 :0]
Ad d res s D e co d in g
C ircu itry as s erts
C S *
