xr
PRELIMINARY
XRT86VL38
REV. P1.0.6
OCTAL T1/E1/J1 FRAMER/LIU COMBO
64
3.
While the microprocessor is placing this address value on the Address Bus, the Address Decoding circuitry
(within the user's system) should assert the CS* (Chip Select) pin of the XRT86VL38 device, by toggling it
"low". This action enables further communication between the microprocessor and the XRT86VL38 Micro-
processor Interface block.
N
OTE
: As the Microprocessor/Address Decoding logic asserts the CS* signal, the user should make sure that the
Microprocessor/Address Decoding circuitry respects the "CS* to Rising edge of PCLK Set-up time" requirements.)
4.
At some time later, the Microprocessor should toggle the "DBEN*" (OE*) input pin "low". This step will
enable the output drivers of the Bi-directional Data Bus pins (D[7:0]). Once the Microprocessor does this,
(and once the Microprocessor Interface samples the "OE*" input pin being at a logic "low" upon a given ris-
ing edge of PCLK) then the Microprocessor Interface (of the XRT86VL38 device) will proceed to place the
contents of the "target" address location (within the XRT86VL38 device) onto the Bi-Directional Data Bus.
5.
Immediately after the microprocessor toggles the "DBEN*" (OE*) input pin "low", the XRT86VL38 device
will continue to drive the "RDY*/DTACK*/RDY output pin "low". The XRT86VL38 device does this in order
to inform the microprocessor that the data (to be read from the data bus) is "NOT READY" to be latched
into the microprocessor. In this, case the microprocessor should continue to hold the "DBEN*" input pin
"low" until it samples the "RDY*/DTACK*/RDY" output pin being at a logic "high".
6.
After some settling time, the data on the bi-directional data bus will stabilize and can be read by the micro-
processor. The XRT86VL38 device will indicate that this data can be read by asserting the RDY*/DTACK*/
RDY (READY) output signal (by toggling it "low"). NOTE: The Microprocessor Interface will update the
state of the RDY signal upon the rising edge of PCLK.
7.
After the microprocessor detects the RDY*/DTACK*/RDY signal (from the XRT86VL38 device) toggling
"low" it can terminate the Read Cycle by toggling the "DBEN*" (OE*) input pin "high".
Figure 9presents a timing diagram that illustrates the behavior of the Microprocessor Interface signals during a
"PowerPC 403" Read Operation
3.3.2
The PowerPC 403 Write-Cycle
F
IGURE
9. P
OWER
PC M
ODE
I
NTERFACE
S
IGNALS
D
URING
R
EAD
O
PERATIONS
PCLK
CS*
R/W*
A[14:0]
D[7:0]
WE*
OE*
RDY
Target Address
Valid Data
Microprocessor places “target”
Address on A[14:0]
Microprocessor sets R/W*
To logic “High” to denote
READ Operation
Microprocessor asserts OE* (DBEN)
Here to initiate READ Operation
XRT86VL38 responds by placing
Valid Data on Data Bus, and by
Asserting RDY
READ Operation
Is terminated
Here
XRT86VL38 samples
A[14:0] here
XRT86VL38 samples
OE* Here
