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System Debug

11-10

ARM DDI 0337G

Non-Confidential

Unrestricted Access

•

COMP is the matching comparator. See Table 11-3.

•

HADDR[1:0]

is the two

Least Significant Bits

(LSBs) of the original address.

HADDR[1:0]

is always 2’b00 for instruction fetches.

The register address, access type, and Reset state are:

Address

0xE0002004

Access

Read/write

Reset state

This register is not reset

Figure 11-3 shows the bit assignments of the Flash Patch Remap Register.

Figure 11-3 Flash Patch Remap Register bit assignments

Table 11-3 COMP mapping

COMP[2:0]

Comparator

Description

000

FP_COMP0

Instruction comparator

001

FP_COMP1

Instruction comparator

010

FP_COMP2

Instruction comparator

011

FP_COMP3

Instruction comparator

100

FP_COMP4

Instruction comparator

101

FP_COMP5

Instruction comparator

110

FP_COMP6

Literal comparator

111

FP_COMP7

Literal comparator

Reserved

29 28

REMAP

Reserved

Summary of Contents for Cortex-M3 DesignStart

Page 2: ...limited to implied warranties of merchantability or fitness for purpose are excluded This document is intended only to assist the reader in the use of the product ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document or any error or omission in such information or any incorrect use of the product Where the term ARM is used it means ARM or a...

Page 3: ...7G Copyright 2005 2008 ARM Limited All rights reserved iii Unrestricted Access Confidential Product Status The information in this document is Final information on a developed product Web Address http www arm com ...

Page 5: ...1 About the processor 1 2 1 2 Components hierarchy and implementation 1 4 1 3 Execution pipeline stages 1 12 1 4 Prefetch Unit 1 14 1 5 Branch target forwarding 1 15 1 6 Store buffers 1 18 1 7 Product revisions 1 19 Chapter 2 Programmer s Model 2 1 About the programmer s model 2 2 2 2 Privileged access and user access 2 3 2 3 Registers 2 4 2 4 Data types 2 10 2 5 Memory formats 2 11 2 6 Instructio...

Page 6: ... 9 Resets 5 20 5 10 Exception control transfer 5 24 5 11 Setting up multiple stacks 5 25 5 12 Abort model 5 27 5 13 Activation levels 5 32 5 14 Flowcharts 5 34 Chapter 6 Clocking and Resets 6 1 Clocking 6 2 6 2 Resets 6 4 6 3 Cortex M3 reset modes 6 5 Chapter 7 Power Management 7 1 About power management 7 2 7 2 System power management 7 3 Chapter 8 Nested Vectored Interrupt Controller 8 1 About t...

Page 7: ...ICode bus interface 12 4 12 4 DCode bus interface 12 6 12 5 System interface 12 7 12 6 Unifying the code buses 12 9 12 7 External private peripheral interface 12 10 12 8 Access alignment 12 11 12 9 Unaligned accesses that cross regions 12 12 12 10 Bit band accesses 12 13 12 11 Write buffer 12 14 12 12 Memory attributes 12 15 12 13 AHB timing characteristics 12 16 Chapter 13 Debug Port 13 1 About t...

Page 8: ...ng 18 1 About instruction timing 18 2 18 2 Processor instruction timings 18 3 18 3 Load store timings 18 7 Chapter 19 AC Characteristics 19 1 Processor timing parameters 19 2 Appendix A Signal Descriptions A 1 Clocks A 2 A 2 Resets A 3 A 3 Miscellaneous A 4 A 4 Interrupt interface A 6 A 5 Low power interface A 7 A 6 ICode interface A 8 A 7 DCode interface A 9 A 8 System bus interface A 10 A 9 Priv...

Page 9: ...truction summary 2 16 Table 3 1 NVIC registers 3 2 Table 3 2 Core debug registers 3 5 Table 3 3 Flash patch register summary 3 6 Table 3 4 DWT register summary 3 7 Table 3 5 ITM register summary 3 9 Table 3 6 AHB AP register summary 3 10 Table 3 7 Summary of Debug interface port registers 3 10 Table 3 8 MPU registers 3 11 Table 3 9 TPIU registers 3 12 Table 3 10 ETM registers 3 13 Table 4 1 Memory...

Page 10: ...ble 8 9 Interrupt Clear Enable Register bit assignments 8 14 Table 8 10 Interrupt Set Pending Register bit assignments 8 15 Table 8 11 Interrupt Clear Pending Registers bit assignments 8 16 Table 8 12 Active Bit Register bit assignments 8 16 Table 8 13 Interrupt Priority Registers 0 31 bit assignments 8 18 Table 8 14 CPUID Base Register bit assignments 8 18 Table 8 15 Interrupt Control State Regis...

Page 11: ... assignments 11 19 Table 11 9 DWT CPI Count Register bit assignments 11 20 Table 11 10 DWT Exception Overhead Count Register bit assignments 11 21 Table 11 11 DWT Sleep Count Register bit assignments 11 22 Table 11 12 DWT LSU Count Register bit assignments 11 23 Table 11 13 DWT Fold Count Register bit assignments 11 23 Table 11 14 DWT Program Counter Sample Register bit assignments 11 24 Table 11 ...

Page 12: ...pcode sequence 15 11 Table 16 1 AHB interface ports 16 3 Table 17 1 Trace out port signals 17 5 Table 17 2 ATB port signals 17 6 Table 17 3 Miscellaneous configuration inputs 17 6 Table 17 4 APB interface 17 7 Table 17 5 TPIU registers 17 8 Table 17 6 Async Clock Prescaler Register bit assignments 17 10 Table 17 7 Selected Pin Protocol Register bit assignments 17 11 Table 17 8 Formatter and Flush ...

Page 13: ...19 15 HTM interface output ports timing parameters 19 9 Table 19 16 Test output ports timing parameters 19 10 Table A 1 Clock signals A 2 Table A 2 Reset signals A 3 Table A 3 Miscellaneous signals A 4 Table A 4 Interrupt interface signals A 6 Table A 5 Low power interface signals A 7 Table A 6 ICode interface A 8 Table A 7 DCode interface A 9 Table A 8 System bus interface A 10 Table A 9 Private ...

Page 15: ...tus Register 2 8 Figure 2 5 Little endian and big endian memory formats 2 12 Figure 4 1 Processor memory map 4 2 Figure 4 2 Bit band mapping 4 6 Figure 5 1 Stack contents after pre emption 5 11 Figure 5 2 Exception entry timing 5 13 Figure 5 3 Tail chaining timing 5 14 Figure 5 4 Late arriving exception timing 5 15 Figure 5 5 Exception exit timing 5 18 Figure 5 6 Interrupt handling flowchart 5 34 ...

Page 16: ...s 8 34 Figure 8 19 Usage Fault Status Register bit assignments 8 36 Figure 8 20 Hard Fault Status Register bit assignments 8 37 Figure 8 21 Debug Fault Status Register bit assignments 8 39 Figure 8 22 Software Trigger Interrupt Register bit assignments 8 42 Figure 9 1 MPU Type Register bit assignments 9 4 Figure 9 2 MPU Control Register bit assignments 9 5 Figure 9 3 MPU Region Number Register bit...

Page 17: ...h pipeline stalls 15 10 Figure 15 7 Unconditional branch in execute aligned 15 11 Figure 15 8 Unconditional branch in execute unaligned 15 11 Figure 15 9 Example of an opcode sequence 15 13 Figure 17 1 TPIU block diagram non ETM version 17 3 Figure 17 2 TPIU block diagram ETM version 17 4 Figure 17 3 Supported Sync Port Size Register bit assignments 17 10 Figure 17 4 Async Clock Prescaler Register...

Page 19: ...8 ARM Limited All rights reserved xix Unrestricted Access Non Confidential Preface This preface introduces the Cortex M3 Technical Reference Manual TRM It contains the following sections About this book on page xx Feedback on page xxv ...

Page 20: ...d on the Cortex M3 processor Using this book This book is organized into the following chapters Chapter 1 Introduction Read this for a description of the components of the processor and about the processor instruction set Chapter 2 Programmer s Model Read this for a description of the processor register set modes of operation and other information for programming the processor Chapter 3 System Con...

Page 21: ...ponents Chapter 13 Debug Port Read this for a description of the processor debug port and the Serial Wire JTAG Debug Port SWJ DP and Serial Wire Debug Port SW DP Chapter 17 Trace Port Interface Unit Read this chapter to learn about the processor Trace Port Interface Unit TPIU Chapter 12 Bus Interface Read this for a description of the processor bus interfaces Chapter 14 Embedded Trace Macrocell Re...

Page 22: ...tions are italic Highlights important notes introduces special terminology denotes internal cross references and citations bold Highlights interface elements such as menu names Denotes signal names Also used for terms in descriptive lists where appropriate monospace Denotes text that you can enter at the keyboard such as commands file and program names and source code monospace Denotes a permitted...

Page 23: ...ng diagram conventions Signals The signal conventions are Signal level The level of an asserted signal depends on whether the signal is active HIGH or active LOW Asserted means HIGH for active HIGH signals LOW for active LOW signals Lower case n At the start or end of a signal name denotes an active LOW signal Prefix A Denotes global Advanced eXtensible Interface AXI signals Prefix AR Denotes AXI ...

Page 24: ...n ARM publications This book contains information that is specific to this product See the following documents for other relevant information ARMv7 M Architecture Reference Manual ARM DDI 0403 ARM AMBA 3 AHB Lite Protocol v1 0 ARM IHI 0033 ARM CoreSight Components Technical Reference Manual ARM DDI 0314 ARM Debug Interface v5 Architecture Specification ARM IHI 0031 ARM Embedded Trace Macrocell Arc...

Page 25: ... this product contact your supplier and give The product name The product revision or version An explanation with as much information as you can provide Include symptoms if appropriate Feedback on this manual If you have any comments on this book send email to errata arm com Give the title the number the page number s to which your comments refer a concise explanation of your comments ARM also wel...

Page 27: ...s chapter introduces the processor and instruction set It contains the following sections About the processor on page 1 2 Components hierarchy and implementation on page 1 4 Execution pipeline stages on page 1 12 Prefetch Unit on page 1 14 Branch target forwarding on page 1 15 Store buffers on page 1 18 Product revisions on page 1 19 ...

Page 28: ... POP for low interrupt latency Automatic processor state saving and restoration for low latency Interrupt Service Routine ISR entry and exit Support for ARMv6 BE8 or LE accesses Support for ARMv6 unaligned accesses Nested Vectored Interrupt Controller NVIC closely integrated with the processor core to achieve low latency interrupt processing Features include External interrupts of 1 to 240 configu...

Page 29: ...ive access transfers for multiprocessor systems Low cost debug solution that features Debug access to all memory and registers in the system including access to memory mapped devices access to internal core registers when the core is halted and access to debug control registers even while SYSRESETn is asserted Serial Wire Debug Port SW DP or Serial Wire JTAG Debug Port SWJ DP debug access or both ...

Page 30: ...so describes the configurable options The main blocks are Processor core on page 1 5 NVIC on page 1 7 Bus matrix on page 1 7 FPB on page 1 8 DWT on page 1 8 ITM on page 1 8 MPU on page 1 9 ETM on page 1 9 AHB AP on page 1 9 AHB Trace Macrocell interface on page 1 9 TPIU on page 1 9 WIC on page 1 10 SW SWJ DP on page 1 10 Interrupts on page 1 11 Observation on page 1 11 ROM table on page 1 11 Figur...

Page 31: ...re Reference Manual for more information Harvard processor architecture enabling simultaneous instruction fetch with data load store Three stage pipeline Single cycle 32 bit multiply Optional ETM Private Peripheral Bus internal Optional DWT Trigger Optional ITM Optional TPIU CM3Core Instr Data Optional FPB Optional MPU Optional AHB AP NVIC SW SWJ DP Bus Matrix APB i f I code bus D code bus System ...

Page 32: ...STM PUSH POP ARMv6 compatible BE8 and LE access support ARMv6 compatible unaligned access support Registers The processor contains 13 general purpose 32 bit registers R0 to R12 Link Register LR Program Counter PC Program Status Register xPSR two banked SP registers Memory interface The processor has a Harvard interface to enable simultaneous instruction fetches with data load stores Memory accesse...

Page 33: ...l chaining of interrupts processor state automatically saved on interrupt entry and restored on interrupt exit with no instruction overhead Chapter 8 Nested Vectored Interrupt Controller describes the NVIC in detail 1 2 3 Bus matrix The bus matrix connects the processor and debug interface to the external buses The bus matrix interfaces to the following external buses ICode bus This is for instruc...

Page 34: ...omparators either remap instruction fetches from code space to system space or perform a hardware breakpoint contain two comparators that can be used for breakpoints only These comparators can remap literal accesses from code space to system space Chapter 11 System Debug describes the FPB 1 2 5 DWT You can configure the implementation to include a DWT If present you can configure the DWT to incorp...

Page 35: ...ents the default memory map attributes Chapter 9 Memory Protection Unit describes the MPU 1 2 8 ETM You can configure the system at implementation to include an ETM This is a low cost trace macrocell that supports instruction trace only Chapter 14 Embedded Trace Macrocell describes the ETM 1 2 9 AHB AP You can configure the implementation to include an AHB AP AHB AP on page 11 39 describes the AHB...

Page 36: ...You can configure the implementation to include a Wake up Interrupt Controller WIC System power management on page 7 3 describes the WIC functionality 1 2 13 SW SWJ DP You can configure the processor to have SW DP or SWJ DP debug port interfaces The debug port provides debug access to all registers and memory in the system including the processor registers The implementation options for the SW SWJ...

Page 37: ...s of interrupt priority at implementation from three to eight bits 1 2 15 Observation You can configure the system at implementation time to enable the observation of some internal signals These include the register bank ports and the instruction in the execute stage of the pipeline 1 2 16 ROM table The ROM table is modified from that described in ROM memory table on page 4 7 if additional debug c...

Page 38: ...e Figure 1 2 shows the pipeline stages of the processor and the pipeline operations that take place at each stage Figure 1 2 Cortex M3 pipeline stages Fetch Instruction Decode and Register Read Fe Address generation unit Branch Shift ALU and Branch Address phase and writeback Data phase Load Store and Branch WR Multiply and Divide De Ex LSU branch result ALU branch not forwarded speculated LSU bra...

Page 39: ...ion memory De Instruction decode generation of LSU address using forwarded register ports and immediate offset or LR register branch forwarding Ex Instruction execute single pipeline with multi cycle stalls LSU address data pipelining to AHB interface multiply divide and ALU with branch result The pipeline structure provides a pipelined 2 cycle memory access with no ALU usage penalty address gener...

Page 40: ... system that can supply one word each cycle The PFU buffers up to three word fetches in its FIFO which means that it can buffer up to three Thumb 32 bit instructions or six Thumb instructions The majority of branches that are generated as the ALU addition of PC plus immediate are generated no later than the decode phase of the branch opcode In the case of conditionally executed branches the addres...

Page 41: ...branch forwarding interface around 10 slower Branch forwarding can be thought of as the internal address generation logic pre registration to the address interface increasing flexibility to the memory controller if you have the timing budget to make use of the information a cycle sooner For example lower MHz power sensitive targets in 0 13u down to 65nm Otherwise you have the flexibility of having...

Page 42: ...rface might be registered To avoid an approximate 25 penalty of adding a wait state you can add a circuit that acts as a single entry prefetcher 1 5 3 One wait state flash Adding wait states to the flash impacts performance of any core You can use a cache to lessen this penalty but this has a dramatic effect on determinism and silicon area A line prefetcher with two line entries can provide compar...

Page 43: ... states flash This is the same as one waitstate cases but with more penalties for branches The extent to which the compiler tools reduce the overhead of branches conditioning loops towards the strengths of the hardware the less the effects of the mismatch between core and memory system speeds A 128 bit interface is better at this point ...

Page 44: ...s common in compiled code This means that the next opcode can overlap the store s data phase reducing the opcode to a single cycle from the perspective of the pipeline The bus matrix interconnect within the processor manages the unaligned behavior of the core and bit banding The bus matrix store buffer is useful for resolving system wait states and unaligned accesses that are split over multiple t...

Page 45: ...terface on page A 14 Addition of SWVMode to the ITM To support SWVMode TPIUACTV and TPIUBAUD have been added as outputs from the TPIU and are inputs to the processor See ITM on page 11 30 CPUID Base Register VARIANT field changed to indicate Rev1 See NVIC register descriptions on page 8 7 Cortex M3 Rev0 Bit band accesses in BE8 mode required access sizes to be byte Cortex M3 Rev1 has been changed ...

Page 46: ...chpoint generation has been made implementation time configurable See DWT on page 11 13 A define has been added to optionally implement architectural clock gating in the ETM For previous releases the architectural clock gate in the ETM was always present DAPCLKEN was required to be a static signal in r0p0 and r1p0 This requirement has been removed for r1p1 SLEEPING signal now suppressed until curr...

Page 47: ... is used An Auxiliary Control Register has been added with new functionality disable bits to stop interruption of load store multiples divides and multiplies stop IT folding disable the write buffers in Cortex M3 for default memory map accesses For details on the Auxiliary Control Register see Auxiliary Control Register on page 8 8 The STKALIGN bit reset value in the Configuration and Control Regi...

Page 49: ...ter 2 Programmer s Model This chapter describes the processor programmer s model It contains the following sections About the programmer s model on page 2 2 Privileged access and user access on page 2 3 Registers on page 2 4 Data types on page 2 10 Memory formats on page 2 11 Instruction set summary on page 2 13 ...

Page 50: ... the ARMv7 M Architecture Reference Manual 2 1 1 Operating modes The processor supports two modes of operation Thread mode and Handler mode Thread mode is entered on Reset and can be entered as a result of an exception return Privileged and User Unprivileged code can run in Thread mode Handler mode is entered as a result of an exception All code is privileged in Handler mode 2 1 2 Operating states...

Page 51: ...l Space SCS When Thread mode has been changed from privileged to user it cannot change itself back to privileged Only a Handler can change the privilege of Thread mode Handler mode is always privileged 2 2 1 Main stack and process stack Out of reset all code uses the main stack An exception handler such as SVC can change the stack used by Thread mode from main stack to process stack by changing th...

Page 52: ...ister set 2 3 1 General purpose registers The general purpose registers r0 r12 have no special architecturally defined uses Most instructions that can specify a general purpose register can specify r0 r12 Low registers Registers r0 r7 are accessible by all instructions that specify a general purpose register High registers Registers r8 r12 are accessible by all 32 bit instructions that specify a g...

Page 53: ...ion return At all other times you can treat r14 as a general purpose register Program counter Register r15 is the Program Counter PC Bit 0 is always 0 so instructions are always aligned to word or halfword boundaries 2 3 2 Special purpose Program Status Registers xPSR Processor status at the system level breaks down into three categories Application PSR Interrupt PSR on page 2 6 Execution PSR on p...

Page 54: ...vation Figure 2 2 shows the bit assignments of the IPSR Figure 2 3 Interrupt Program Status Register bit assignments 31 30 29 28 27 N Z C V 0 Reserved Q 26 Table 2 1 Application Program Status Register bit assignments Field Name Definition 31 N Negative or less than flag 1 result negative or less than 0 result positive or greater than 30 Z Zero flag 1 result of 0 0 nonzero result 29 C Carry borrow...

Page 55: ...d the Thumb state bit T bit Interruptible continuable instruction field Load Multiple LDM operations and Store Multiple STM operations are interruptible The ICI field of the EPSR holds the information required to continue the load or store multiple from the point that the interrupt occurred If then state field The IT field of the EPSR contain the execution state bits for the If Then instruction Ta...

Page 56: ...Definition 31 27 Reserved 26 25 15 10 ICI Interruptible continuable instruction bits When an interrupt occurs during an LDM or STM operation the multiple operation stops temporarily The EPSR uses bits 15 12 to store the number of the next register operand in the multiple operation After servicing the interrupt the processor returns to the register pointed to by 15 12 and resumes the multiple opera...

Page 57: ... register in the list the base register changes to the loaded value An LDM STM is restarted rather than continued if the LDM STM faults the LDM STM is inside an IT If an LDM has completed a base load it is continued from before the base load Saved xPSR bits On entering an exception the processor saves the combined information from the three status registers on the stack The stacked xPSR also conta...

Page 58: ...nfidential Unrestricted Access 2 4 Data types The processor supports the following data types 32 bit words 16 bit halfwords 8 bit bytes Note Memory systems are expected to support all data types In particular the system must support subword writes without corrupting neighboring bytes in that word ...

Page 59: ... a word is the most significant The byte at address 0 of the memory system connects to data lines 7 0 In big endian format the byte with the lowest address in a word is the most significant byte of the word The byte with the highest address in a word is the least significant The byte at address 0 of the memory system connects to data lines 31 24 Figure 2 5 on page 2 12 shows the difference between...

Page 60: ...at address 8 Byte 3 at address 8 Byte 2 at address 9 Byte 1 at address A Byte 0 at address B Word at address C Byte 3 at address C Byte 2 at address D Byte 1 at address E Byte 0 at address F Halfword 1 at address E Halfword 0 at address C Halfword 1 at address A Halfword 0 at address 8 Halfword 1 at address 6 Halfword 0 at address 4 Halfword 1 at address 2 Halfword 0 at address 0 Little endian dat...

Page 61: ...d low register value to low register value ADD Rd Rn Rm Add high register value to low or high register value ADD Rd Rm Add 4 immediate 8 bit value with PC to register ADD Rd PC immed_8 4 Add 4 immediate 8 bit value with SP to register ADD Rd SP immed_8 4 Add 4 immediate 7 bit value to SP ADD SP immed_7 4 Bitwise AND register values AND Rd Rm Arithmetic shift right by immediate number ASR Rd Rm im...

Page 62: ...fset LDR Rd Rn immed_5 4 Load memory word from base register address register offset LDR Rd Rn Rm Load memory word from PC address 8 bit immediate offset LDR Rd PC immed_8 4 Load memory word from SP address 8 bit immediate offset LDR Rd SP immed_8 4 Load memory byte 7 0 from register address 5 bit immediate offset LDRB Rd Rn immed_5 Load memory byte 7 0 from register address register offset LDRB R...

Page 63: ...and copy to register REV Rd Rn Reverse bytes in two halfwords and copy to register REV16 Rd Rn Reverse bytes in low halfword 15 0 sign extend and copy to register REVSH Rd Rn Rotate right by amount in register ROR Rd Rs Subtract register value and C flag from register value SBC Rd Rm Send event SEV c Store multiple register words to sequential memory locations STMIA Rn registers Store register wor...

Page 64: ...value TST Rn Rm Extract byte 7 0 from register move to register and zero extend to 32 bits UXTB Rd Rm Extract halfword 15 0 from register move to register and zero extend to 32 bits UXTH Rd Rm Wait for event WFE c Wait for interrupt WFI c Table 2 4 16 bit Cortex M3 instruction summary continued Operation Assembler Table 2 5 32 bit Cortex M3 instruction summary Operation Assembler Add register valu...

Page 65: ...clusive access CLREX c Return number of leading zeros in register value CLZ W Rd Rn Compare register value with two s complement of immediate 12 bit value CMN W Rn modify_constant immed_12 Compare register value with two s complement of shifted register value CMN W Rn Rm shift Compare register value with immediate 12 bit value CMP W Rn modify_constant immed_12 Compare register value with shifted r...

Page 66: ...LSL shift Memory word to PC from register address shifted left by 0 1 2 or 3 places LDR W PC Rn Rm LSL shift Memory word from PC address immediate 12 bit offset LDR W Rxf PC offset_12 Memory word to PC from PC address immediate 12 bit offset LDR W PC PC offset_12 Memory byte 7 0 from base register address immediate 12 bit offset LDRB W Rxf Rn offset_12 Memory byte 7 0 from base register address im...

Page 67: ... base register address immediate 8 bit offset postindexed LDRH W Rxf Rn offset_8 Memory halfword 15 0 from register address shifted left by 0 1 2 or 3 places LDRH W Rxf Rn Rm LSL shift Memory halfword from PC address immediate 12 bit offset LDRH W Rxf PC offset_12 Memory signed byte 7 0 from base register address immediate 12 bit offset LDRSB W Rxf Rn offset_12 Memory signed byte 7 0 from base reg...

Page 68: ...W Rd Rn Rm Racc Move immediate 12 bit value to register MOV S W Rd modify_constant immed_12 Move shifted register value to register MOV S W Rd Rm shift Move immediate 16 bit value to top halfword 31 16 of register MOVT W Rd immed_16 Move immediate 16 bit value to bottom halfword 15 0 of register and clear top halfword 31 16 MOVW W Rd immed_16 Move to register from status MRS c Rd psr Move to statu...

Page 69: ...vide SDIV c Rd Rn Rm Send event SEV c Multiply signed words and add signed extended value to 2 register value SMLAL W RdLo RdHi Rn Rm Multiply two signed register values SMULL W RdLo RdHi Rn Rm Signed saturate SSAT W c Rd imm Rn shift Multiple register words to consecutive memory locations STM IA DB W Rn registers Register word to register address immediate 12 bit offset STR W Rxf Rn offset_12 Reg...

Page 70: ...ressed STREXB c Rd Rt Rn Store register exclusive halfword derives an address from a base register value and stores a halfword from a register to memory if the executing processor has exclusive access to the memory addressed STREXH c Rd Rt Rn Register halfword 15 0 to register address immediate 12 bit offset STRH W Rxf Rn offset_12 Register halfword 15 0 to register address shifted by 0 1 2 or 3 p...

Page 71: ...er value with shifted register value TST W Rn Rm shift Copy bit field from register value to register and zero extend to 32 bits UBFX W Rd Rn lsb width Unsigned divide UDIV c Rd Rn Rm Multiply two unsigned register values and add to a 2 register value UMLAL W RdLo RdHi Rn Rm Multiply two unsigned register values UMULL W RdLo RdHi Rn Rm Unsigned saturate USAT c Rd imm Rn shift Copy unsigned byte to...

Page 73: ...RM Limited All rights reserved 3 1 Unrestricted Access Non Confidential Chapter 3 System Control This chapter describes the registers that program the processor It contains the following section Summary of processor registers on page 3 2 ...

Page 74: ...s a summary of the Nested Vectored Interrupt Controller NVIC registers For a detailed description of the NVIC registers see Chapter 8 Nested Vectored Interrupt Controller Table 3 1 NVIC registers Name of register Type Address Reset value Interrupt Control Type Register Read only 0xE000E004 a Auxiliary Control Register Read write 0xE000E008 0x0 SysTick Control and Status Register Read write 0xE000E...

Page 75: ...q 224 to 239 Clear Pending Register Read write 0xE000E29C 0x00000000 Irq 0 to 31 Active Bit Register Read only 0xE000E300 0x00000000 Irq 224 to 239 Active Bit Register Read only 0xE000E31C 0x00000000 Irq 0 to 3 Priority Register Read write 0xE000E400 0x00000000 Irq 236 to 239 Priority Register Read write 0xE000E4EC 0x00000000 CPUID Base Register Read only 0xE000ED00 0x412FC230 Interrupt Control St...

Page 76: ... Register Read write 0xE000ED34 Unpredictable Bus Fault Address Register Read write 0xE000ED38 Unpredictable Auxiliary Fault Status Register Read write 0xE000ED3C 0x00000000 PFR0 Processor Feature register0 Read only 0xE000ED40 0x00000030 PFR1 Processor Feature register1 Read only 0xE000ED44 0x00000200 DFR0 Debug Feature register0 Read only 0xE000ED48 0x00100000 AFR0 Auxiliary Feature register0 Re...

Page 77: ... Bits 15 8 PID1 Read only 0xE000EFE4 0xB0 Peripheral identification register Bits 23 16 PID2 Read only 0xE000EFE8 0x2B Peripheral identification register Bits 31 24 PID3 Read only 0xE000EFEC 0x00 Component identification register Bits 7 0 CID0 Read Only 0xE000EFF0 0x0D Component identification register Bits 15 8 CID1 Read only 0xE000EFF4 0xE0 Component identification register Bits 23 16 CID2 Read ...

Page 78: ...eset to 1 b0 Flash Patch Control Register FP_REMAP Read write 0xE0002004 Flash Patch Remap Register FP_COMP0 Read write 0xE0002008 Bit 0 is reset to 1 b0 Flash Patch Comparator Registers FP_COMP1 Read write 0xE000200C Bit 0 is reset to 1 b0 Flash Patch Comparator Registers FP_COMP2 Read write 0xE0002010 Bit 0 is reset to 1 b0 Flash Patch Comparator Registers FP_COMP3 Read write 0xE0002014 Bit 0 is...

Page 79: ...egister summary Name Type Address Reset value Description DWT_CTRL Read write 0xE0001000 0x40000000 DWT Control Register DWT_CYCCNT Read write 0xE0001004 0x00000000 DWT Current PC Sampler Cycle Count Register DWT_CPICNT Read write 0xE0001008 DWT Current CPI Count Register DWT_EXCCNT Read write 0xE000100C DWT Current Interrupt Overhead Count Register DWT_SLEEPCNT Read write 0xE0001010 DWT Current S...

Page 80: ...write 0xE0001054 DWT Mask Registers DWT_FUNCTION3 Read write 0xE0001058 0x00000000 DWT Function Registers PID4 Read only 0xE0001FD0 0x04 Value 0x04 PID5 Read only 0xE0001FD4 0x00 Value 0x00 PID6 Read only 0xE0001FD8 0x00 Value 0x00 PID7 Read only 0xE0001FDC 0x00 Value 0x00 PID0 Read only 0xE0001FE0 0x02 Value 0x02 PID1 Read only 0xE0001FE4 0xB0 Value 0xB0 PID2 Read only 0xE0001FE8 0x0B0 Value 0x2B...

Page 81: ...ster Read write 0xE0000E80 0x00000000 Integration Write Write only 0xE0000EF8 0x00000000 Integration Read Read only 0xE0000EFC 0x00000000 Integration Mode Control Read write 0xE0000F00 0x00000000 Lock Access Register Write only 0xE0000FB0 0x00000000 Lock Status Register Read only 0xE0000FB4 0x00000003 PID4 Read only 0xE0000FD0 0x00000004 PID5 Read only 0xE0000FD4 0x00000000 PID6 Read only 0xE0000F...

Page 82: ...rs see Chapter 13 Debug Port Table 3 6 AHB AP register summary Name Type Address Reset value Control and Status Word Read write 0x00 See Register Transfer Address Read write 0x04 Data Read write Read write 0x0C Banked Data 0 Read write 0x10 Banked Data 1 Read write 0x14 Banked Data 2 Read write 0x18 Banked Data 3 Read write 0x1C Debug ROM Address Read only 0xF8 0xE000E000 Identification Register R...

Page 83: ... Name Type Address Reset value MPU Type Register Read Only 0xE000ED90 0x00000800 MPU Control Register Read Write 0xE000ED94 0x00000000 MPU Region Number register Read Write 0xE000ED98 MPU Region Base Address register Read Write 0xE000ED9C MPU Region Attribute and Size registers Read Write 0xE000EDA0 MPU Alias 1 Region Base Address register Alias of D9C 0xE000EDA4 MPU Alias 1 Region Attribute and S...

Page 84: ...Flush Status Register Read only 0xE0040300 0x08 Formatter and Flush Control Register Read write 0xE0040304 0x00 or 0x102 Formatter Synchronization Counter Register Read only 0xE0040308 0x00 Integration Register ITATBCTR2 Read only 0xE0040EF0 0x0 Integration Register ITATBCTR0 Read only 0xE0040EF8 0x0 Integration Mode Control Register Read write 0xE0040F00 0x0 Integration register FIFO data 0 Read ...

Page 85: ... register Type Address Reset value Table 3 10 ETM registers Name Type Address Present ETM Control Read write 0xE0041000 Yes Configuration Code Read only 0xE0041004 Yes Trigger event Write only 0xE0041008 Yes ASIC Control Write only 0xE004100C No ETM Status Read only or read write 0xE0041010 Yes System Configuration Read only 0xE0041014 Yes TraceEnable Write only 0xE0041018 0xE004101C No TraceEnabl...

Page 86: ...E Read write 0xE00411F0 Yes Embedded ICE Behavior Control Write only 0xE00411F4 No CoreSight Trace ID Read write 0xE0041200 Yes OS Save Restore Write only 0xE0041304 0xE0041308 No ITMISCIN Read only 0xE0041EE0 Yes ITTRIGOUT Write only 0xE0041EE8 Yes ITATBCTR2 Read only 0xE0041EF0 Yes ITATBCTR0 Write only 0xE0041EF8 Yes Integration Mode Control Read write 0xE0041F00 Yes Claim Tag Read write 0xE0041...

Page 87: ...041FE0 Yes Peripheral ID 1 Read only 0xE0041FE4 Yes Peripheral ID 2 Read only 0xE0041FE8 Yes Peripheral ID 3 Read only 0xE0041FEC Yes Component ID 0 Read only 0xE0041FF0 Yes Component ID 1 Read only 0xE0041FF4 Yes Component ID 2 Read only 0xE0041FF8 Yes Component ID 3 Read only 0xE0041FFC Yes Table 3 10 ETM registers continued Name Type Address Present ...

Page 89: ...d 4 1 Unrestricted Access Non Confidential Chapter 4 Memory Map This chapter describes the processor fixed memory map and its bit banding feature It contains the following sections About the memory map on page 4 2 Bit banding on page 4 5 ROM memory table on page 4 7 ...

Page 90: ...000000 0x5FFFFFFF 0x60000000 0x3FFFFFFF 0x40000000 0x1FFFFFFF 0x20000000 0x00000000 ROM Table ETM TPIU Reserved System Control Space Reserved FPB DWT ITM External PPB 0xE00FFFFF 0xE0042000 0xE0041000 0xE0040000 0xE003FFFF 0xE000F000 0xE000E000 0xE0003000 0xE0002000 0xE00FF000 0x40000000 Bit band region Bit band alias 32MB 1MB 31MB 0x40100000 0x42000000 0x43FFFFFF 0x41FFFFFF 0xE0001000 0xE0000000 P...

Page 91: ...sses are not aliases External RAM Instruction fetches and data accesses are performed over the system bus External Device Instruction fetches and data accesses are performed over the system bus Private Peripheral Bus Accesses to Instrumentation Trace Macrocell ITM Nested Vectored Interrupt Controller NVIC Flashpatch and Breakpoint FPB Data Watchpoint and Trace DWT Memory Protection Unit MPU are pe...

Page 92: ...s Name Region Device type XN Cache Code 0x00000000 0x1FFFFFFF Normal WT SRAM 0x20000000 0x3FFFFFFF Normal WBWA SRAM_1M 0000000 SRAM_31M 0100000 SRAM_bitband 2000000 Internal SRAM 4000000 Peripheral 0x40000000 0x5FFFFFFF Device XN Periph_1IM 0000000 Periph_31IM 0100000 Periph_bit band 2000000 Internal Peripheral 4000000 External RAM 0x60000000 0x7FFFFFFF Normal WBWA External RAM 0x80000000 0x9FFFFF...

Page 93: ..._number 4 bit_word_addr bit_band_base bit_word_offset where Bit_word_offset is the position of the target bit in the bit band memory region Bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit Bit_band_base is the starting address of the alias region Byte_offset is the number of the byte in the bit band region that contains the targeted bit Bit_number i...

Page 94: ...ame effect as writing 0xFF Writing 0x00 has the same effect as writing 0x0E Reading a word in the alias region returns either 0x01 or 0x00 A value of 0x01 indicates that the targeted bit in the bit band region is set A value of 0x00 indicates that the targeted bit is clear Bits 31 1 are zero 4 2 2 Directly accessing a bit band region You can directly access the bit band region with normal reads an...

Page 95: ...ation Trace block at 0xE0000000 Value has bit 0 set if ITM is present 0x010 0xFFF41002 or 003 if present TPIU Points to the TPIU Value has bit 0 set to 1 if TPIU is present TPIU is at 0xE0040000 0x014 0xFFF42002 or 003 if present ETM Points to the ETM Value has bit 0 set to 1 if ETM is present ETM is at 0xE0041000 0x018 0 End Marks the end of the ROM table If CoreSight components are added they ar...

Page 96: ... 8 Copyright 2005 2008 ARM Limited All rights reserved ARM DDI 0337G Non Confidential Unrestricted Access 0xFF4 0x10 CID1 0xFF8 0x05 CID2 0xFFC 0xB1 CID3 Table 4 3 ROM table continued Offset Value Name Description ...

Page 97: ...sections About the exception model on page 5 2 Exception types on page 5 4 Exception priority on page 5 6 Privilege and stacks on page 5 9 Pre emption on page 5 11 Tail chaining on page 5 14 Late arriving on page 5 15 Exit on page 5 17 Resets on page 5 20 Exception control transfer on page 5 24 Setting up multiple stacks on page 5 25 Abort model on page 5 27 Activation levels on page 5 32 Flowchar...

Page 98: ...ding of the vector table entry that contains the ISR address in code memory or data SRAM This is performed in parallel to the state saving Note Vector table entries are ARM Thumb interworking compatible This causes bit 0 of the vector value to load into the EPSR T bit on exception entry Creating a table entry with bit 0 clear generates an INVSTATE fault on the first instruction of the handler corr...

Page 99: ...Unrestricted Access Non Confidential Note The number of interrupts and bits of interrupt priority are configured during implementation Software can choose only to enable a subset of the configured number of interrupts and can choose how many bits of the configured priorities to use ...

Page 100: ...synchronously or asynchronously is also shown The exact meaning and use of priorities is explained in Exception priority on page 5 6 Table 5 1 Exception types Exception type Position Priority Description 0 Stack top is loaded from first entry of vector table on reset Reset 1 3 highest Invoked on power up and warm reset On first instruction drops to lowest priority Thread mode This is asynchronous ...

Page 101: ...by software SysTick 15 Configurable System tick timer has fired This is asynchronous External Interrupt 16 and more Configurable Asserted from outside the core INTISR 239 0 and fed through the NVIC prioritized These are all asynchronous a You can change the priority of this exception See System Handler Priority Registers bit assignments on page 8 29 Settable is an NVIC priority value of 0 to N whe...

Page 102: ...stem bus or the ICode bus depending on where the vector table is located see Vector Table Offset Register on page 8 21 Tail chain A mechanism used by the processor to speed up interrupt servicing On completion of an ISR if there is a pending interrupt of higher priority than the ISR or thread that is being returned to the stack pop is skipped and control is transferred to the new ISR Return With n...

Page 103: ...errupt with the lowest interrupt number takes precedence For example if both IRQ 0 and IRQ 1 are priority level 1 then IRQ 0 has higher priority than IRQ 1 For more information on the PRI_N fields see Interrupt Priority Registers on page 8 17 5 3 2 Priority grouping To increase priority control in systems with large numbers of interrupts the NVIC supports priority grouping You can use the PRIGROUP...

Page 104: ...ity and PRI_N 3 0 is 4 b0000 An interrupt can pre empt another interrupt in progress only if its pre emption priority is higher than that of the interrupt in progress For more information on priority optimizations priority level grouping and priority masking see the ARMv7 M Architecture Reference Manual Table 5 3 Priority grouping Interrupt priority level field PRI_N 7 0 PRIGROUP 2 0 Binary point ...

Page 105: ...ss Appropriate EXC_RETURN values can also set this bit when exiting an ISR An exception that pre empts a user thread saves the context of the user thread on the stack that the Thread mode is using All exceptions use the main stack for their own local variables Using the process stack for the Thread mode and the main stack for exceptions supports Operating System OS scheduling To reschedule the ker...

Page 106: ...l other concepts in ARMv7 M Code can be privileged with full access rights or unprivileged with limited access rights Access rights affect ability to Use or not use certain instructions such as MSR fields Access System Control Space SCS registers Access memory or peripherals based on system design The processor indicates to the system whether the code making an access is privileged and so the syst...

Page 107: ... LR The SP is decremented by eight words by the completion of the stack push Figure 5 1 shows the contents of the stack after an exception pre empts the current program flow Figure 5 1 Stack contents after pre emption Note Figure 5 1 shows the order on the stack If STKALIGN is set in the Configuration Control Register then an extra word can be inserted before the stacking takes place See Configura...

Page 108: ...on the ICode bus can be done simultaneously with register pushes on the DCode bus Read SP from vector table No On Reset only updates SP to top of stack from vector table Other exceptions do not modify SP except to select stack push and pop Update PC No Updates PC with vector table read location Late arriving exceptions cannot be processed until the first instruction starts to execute Load pipeline...

Page 109: ...asserted throughout the duration of the ISR CURRPRI becomes valid when ETMINTSTAT indicates that the ISR has been entered 3 b001 ETMINTNUM 8 0 indicates the number of the active interrupt ETMINTNUM remains asserted throughout the duration of the ISR ETMINTNUM becomes valid when ETMINTSTAT indicates that the ISR has been entered 3 b001 Prior to that it indicates which ISR is being fetched Figure 5 ...

Page 110: ...rrupt The ISR that is tail chained into starts execution six cycles after exiting the previous ISR Figure 5 3 Tail chaining timing On return from the last ISR INTISR 2 is of higher priority than any stacked ISR or other pended interrupt and so the processor tail chains to the ISR corresponding to INTISR 2 In the cycle that the ISR for INTISR 2 enters execute ETMINSTAT 2 0 indicates that the ISR ha...

Page 111: ...errupts Figure 5 4 Late arriving exception timing In Figure 5 4 INTISR 8 pre empts INTISR 2 The state saving for INTISR 2 is already done and is not required to be repeated Figure 5 4 shows the latest point at which INTISR 8 can pre empt before the first instruction of the ISR for INTISR 2 enters Execute stage A higher priority interrupt after that point is managed as a pre emption CURRPRI 7 0 HRD...

Page 112: ...s received and the processor then initiates the vector fetch for INTISR 9 A higher priority interrupt after that point is managed as pre emption In the cycle that the ISR for INTISR 9 enters execute ETMINSTAT 2 0 indicates that the ISR has been entered 3 b001 This is a 1 cycle pulse CURRPRI 7 0 indicates the priority of the active interrupt CURRPRI remains asserted throughout the duration of the I...

Page 113: ...igher priority than the highest priority pending exception returning to the Thread mode if there are no pending or stacked exceptions Table 5 5 describes the postamble sequence Figure 5 5 on page 5 18 shows an example of exception exit timing Table 5 5 Exception exit steps Action Description Pop eight registers Pops PC xPSR r0 r1 r2 r3 r12 and LR from stack selected by EXC_RETURN and adjusts SP if...

Page 114: ...ception occurs during the stack pop the processor abandons the stack pop rewinds the stack pointer and services the exception as a tail chain case 5 8 2 Returning the processor from an ISR Exception returns occur when one of the following instructions loads a value of 0xFFFFFFFX into the PC POP LDM which includes loading the PC LDR with PC as a destination BX with any register CLK HADDRI 31 0 HRDA...

Page 115: ...by any other instruction the value is treated as an address not as a special value This address range is defined to have Execute Never XN permissions and results in a MemManage fault Table 5 6 Exception return behavior EXC_RETURN 3 0 Description 0bXXX0 Reserved 0b0001 Return to Handler mode Exception return gets state from the main stack On return execution uses the main stack 0b0011 Reserved 0b01...

Page 116: ... regardless of location points to all mask enabled exceptions Also the SVCall ISR location is populated if the SVC instruction is used An example of a full vector table unsigned int stack_base STACK_SIZE void ResetISR void void NmiISR void ISR_VECTOR_TABLE vector_table_at_0 stack_base sizeof stack_base ResetISR NmiSR FaultISR Table 5 7 Reset actions Action Description NVIC resets holds core in res...

Page 117: ... 5 8 A C C runtime can perform the first three steps and then call main Table 5 8 Reset boot up behavior Action Description Initialize variables Any global static variables must be setup This includes initializing the BSS variable to 0 and copying initial values from ROM to RAM for non constant variables Setup stacks If more than one stack is be used the other banked SPs must be initialized The cu...

Page 118: ...enable interrupts nvic_regs NV_SLEEP NVSLEEP_ON_EXIT will not normally come back after 1st exception while 1 wfi Setup interrupts Setup priority levels and masks Enable interrupts Enable interrupts Enable the interrupt processing in the NVIC It is not desirable to have these occur while they are being enabled If there are more than 32 interrupts it takes more than one Set Enable Register PRIMASK c...

Page 119: ...ttention void reset do setup work initialize variables initialize runtime if wanted setup peripherals etc nvic INT_ENA 1 enable interrupts while 1 We are slept until an exception clears sleep on exit state so that we can post process cleanup nvic_regs NV_SLEEP NVSLEEP_ON_EXIT while nvic_regs NV_SLEEP NVSLEEP_ON_EXIT wfi sleep now wait for interrupt which clears do some post exception checking clea...

Page 120: ...on bus permission and Interruptible Continuable Instruction ICI rules For more information on ICI rules see the ARMv7 M Architecture Reference Manual Exception entry This is a late arriving exception If it has higher priority than the exception being entered then the processor cancels the exception entry actions and takes the late arriving exception Late arriving results in a decision change vecto...

Page 121: ...uence 1 Call setup routine to a Set up other stacks using MSR b Enable the MPU to support base regions if any c Invoke all boot routines d Return from setup routine 2 Change Thread mode to unprivileged 3 Use SVC to invoke the kernel Then the kernel a Starts threads b Uses MRS to read the SP for the current user thread and save it in its TCB c Uses MSR to set the SP for the next thread This is usua...

Page 122: ...r to old Thread Control Block STR r12 r0 Store SP into Thread Control Block LDR r0 NewPSPValue Get pointer to new Thread Control Block LDR r12 r0 Acquire new Process SP LDMIA r12 r4 r11 LR Restore non stacked registers MSR PSP r12 Set PSP to R12 BX lr Return back to Thread Note In Example 5 4 on page 5 25 and Example 5 5 the only time the decision to move Thread from MSP to PSP can be made or the ...

Page 123: ...than Reset NMI or another Hard Fault Note Code that uses FAULTMASK acts as a Hard Fault and so follows the same rules as a Hard Fault Secondary bus faults do not escalate because a pre empting fault of the same type cannot pre empt itself This means that if a corrupted stack causes a fault the fault handler still executes even though the stack pushes for the handler failed The fault handler can op...

Page 124: ...e bus error returned INTERR uCode stack pop error MUNSKERR MemManage Failure when restoring context using hardware MPU access violation INTERR Escalated to Hard Fault FORCED HardFault Fault occurred and handler is equal or higher priority than current including fault within fault when priority does not enable or Configurable fault disabled Includes SVC BKPT and other kinds of faults HARDERR MPU mi...

Page 125: ...tes after return from exception including inter working states STATERR Return to PC EXC_RETURN when not enabled or with invalid magic number INVPC UsageFault Illegal exit caused either by an illegal EXC_RETURN value an EXC_RETURNand stackedEPSR value mismatch or an exit while the current EPSR is not contained in the list of currently active exceptions STATERR Illegal unaligned load or store UNALIG...

Page 126: ...ter BFAR Memory Fault Address Register MFAR A flag in the corresponding fault status register indicates when the address in the fault address register is valid Note BFAR and MFAR are the same physical register Because of this the BFARVALID and MFARVALID bits are mutually exclusive Table 5 12 on page 5 31 shows the fault status registers and two fault address registers Table 5 11 Debug faults Fault...

Page 127: ... Non Confidential Table 5 12 Fault status and fault address registers Status Register name Handler Address Register name Description HFSR Hard Fault Escalation and Special MMSR Mem Manage MMAR MPU faults BFSR Bus Fault BFAR Bus faults UFSR Usage Fault Usage fault DFSR Debug Monitor or Halt Debug traps ...

Page 128: ... or process ISR active Asynchronous pre emption level Privileged Main Fault handler active Synchronous pre emption level Privileged Main Reset Thread mode Privileged Main Table 5 14 Exception transitions Active Exception Triggering event Transition type Privilege Stack Reset Reset signal Thread Privileged or user Main or process ISRa or NMIb Set pending software instruction or hardware signal Asyn...

Page 129: ...an or equal to current hard fault PendSV Software pend request Chain Pre empt or tail chain according to priority UsageFault Undefined instruction Synchronous If priority greater than or equal to current hard fault NoCpFault Access to absent CP Synchronous If priority greater than or equal to current hard fault BusFault Memory access error Synchronous If priority greater than or equal to current h...

Page 130: ... Return on page 5 35 5 14 1 Interrupt handling Figure 5 6 shows how instructions execute until pre empted by a higher priority interrupt Figure 5 6 Interrupt handling flowchart Execute instruction No Yes Yes Return from interrupt No Pending interrupt higher priority than active interrupt Reset Load SP and PC from locations 0 4 Yes Pre empt PC at return location No Pending interrupt higher priority...

Page 131: ... 5 7 Pre emption flowchart 5 14 3 Return Figure 5 8 on page 5 36 shows how the processor restores the stacked ISR or tail chains to a late arriving interrupt with higher priority than the stacked ISR Pre empt Read new PC from vector table Push registers r0 r3 r12 LR PC and xPSR onto SP stack Late arriving interrupt Yes No Fill pipeline at PC Late arriving interrupt Yes No Execute instructions Sync...

Page 132: ...Access Figure 5 8 Return from interrupt flowchart Return Adjust stack load pipeline from PC Set LR tail chain to new interrupt Pop next register Execute instructions Late arriving higher priority interrupt Yes Popped last register Yes No No Read new PC from vector table Fill pipeline from PC Execute instructions ...

Page 133: ...rights reserved 6 1 Unrestricted Access Non Confidential Chapter 6 Clocking and Resets This chapter describes the processor clocking and resets It contains the following sections Clocking on page 6 2 Resets on page 6 4 Cortex M3 reset modes on page 6 5 ...

Page 134: ...terface domain of the SWJ DP In JTAG mode this is equivalent to TCK In Serial Wire Mode this is the Serial Wire clock It is asynchronous to all other clocks DBGCLK is the clock for the debug interface domain of SW DP It is asynchronous to the other clocks TRACECLKIN is the reference clock for the Trace Port Interface Unit TPIU It is asynchronous to the other clocks Table 6 1 Cortex M3 processor cl...

Page 135: ...our implementation contains Serial Wire JTAG Debug Port SWJ DP Serial Wire Debug Port SW DP and TPIU blocks respectively Otherwise the clock inputs must be tied off Note The processor also contains a STCLK input This port is not a clock It is a reference input for the SysTick counter and it must be less than half the frequency of FCLK STCLK is synchronized internally by the processor to FCLK ...

Page 136: ...your implementation does not contain SWJ DP this reset must be tied off Table 6 3 Reset inputs Reset input Description PORESETn Resets the entire processor system with the exception of SWJ DP SYSRESETn Resets the entire processor system with the exception of debug logic in the Nested Vectored Interrupt Controller NVIC Flash Patch and Breakpoint FPB Data Watchpoint and Trace DWT Instrumentation Tra...

Page 137: ... reset signals and the combinations and possible applications that you can use them in Note PORESETn resets a superset of the SYSRESETn logic 6 3 1 Power on reset Figure 6 1 on page 6 6 shows the reset signals for the macrocell Table 6 4 Reset modes Reset mode SYSRESETn nTRST PORESETn Application Power on reset x 0 0 Reset at power up full system reset Cold reset System reset 0 x 1 Reset of proces...

Page 138: ...zed within the processor you do not have to synchronize this signal Figure 6 2 shows the application of power on reset Figure 6 3 on page 6 7 shows the reset synchronizers within the processor Figure 6 2 Power on reset It is recommended that you assert the reset signals for at least three HCLK cycles to ensure correct reset behavior Figure 6 3 on page 6 7 shows the internal reset synchronization C...

Page 139: ...SETn must be synchronized external to the processor Figure 6 3 shows the example reset synchronization provided in CortexM3Integration Cortex M3 exports a signal SYSRESETREQ that is asserted when the SYSRESETREQ bit of the Application Interrupt and Reset Control Register is set For example you can use this as an input to a watchdog timer as Figure 6 1 on page 6 6 shows 6 3 3 SWJ DP reset nTRST res...

Page 140: ...asserted with regard to the SWCLKTCK clock because the SWJ DP performs no synchronization 6 3 4 SW DP reset SW DP is reset with DBGRESETn This reset must be synchronized to DBGCLK 6 3 5 Normal operation During normal operation neither processor reset nor power on reset is asserted If the SWJ DP port is not being used the value of nTRST does not matter ...

Page 141: ...ights reserved 7 1 Unrestricted Access Non Confidential Chapter 7 Power Management This chapter describes the processor power management functions It contains the following sections About power management on page 7 2 System power management on page 7 3 ...

Page 142: ...ssor extensively uses gated clocks to disable unused functionality and disables inputs to unused functional blocks so that only actively used logic consumes any dynamic power The ARMv7 M architecture supports system sleep modes that can stop the Cortex M3 and system clocks for greater power reductions These are described in System power management on page 7 3 ...

Page 143: ...hanism Description Sleep now The Wait For Interrupt WFI or the Wait For Event WFE instructions request the sleep now model These instructions cause the Nested Vectored Interrupt Controller NVIC to put the processor into the low power state pending another exception a Sleep on exit When the SLEEPONEXIT bit of the System Control Register is set the processor enters the low power state as soon as it ...

Page 144: ...terrupts the processor must receive the free running FCLK at all times unless the WIC is in use FCLK clocks A small amount of logic in the NVIC that detects interrupts The Data Watchpoint and Trace DWT and Instrumentation Trace Macrocell ITM blocks These blocks can generate trace packets during sleep when so enabled If the TRCENA bit of the Debug Exception and Monitor Control Register is enabled t...

Page 145: ... following cycle SLEEPHOLDACKn is asserted to confirm the extension request When a wake up event occurs SLEEPING is de asserted as normal but SLEEPHOLDACKn remains asserted and the core remains sleeping SLEEPHOLDREQn must be de asserted to enable the core to wake up Halting the core also causes SLEEPHOLDACKn to be de asserted and the sleep mode to be exited as is the case with SLEEPING irrespectiv...

Page 146: ...ic power of the processor while in very deep sleep modes This can be achieved by stopping clocks or removing power from the processor or both When powered off the NVIC is unable to prioritize or detect interrupts This means that knowing when to come out of very deep sleep becomes problematic The Wake up Interrupt Controller WIC provides significantly reduced gate count interrupt detection logic th...

Page 147: ...h occurred while the NVIC was sleeping This enables pulse interrupts to be used in combination with WIC based sleep methods The PMU must assert SLEEPHOLDREQn to prevent the processor from waking up during a power down sequence When it has been acknowledged by SLEEPHOLDACKn then the PMU can proceed to power down the system When the WIC detects a wake up trigger from an interrupt or an event then it...

Page 148: ...re typically inserted by the tools during synthesis SLEEPING WICLOAD SLEEPDEEP WICMASK WICCLEAR nISOLATE nRETAIN PWRUP WICINT WAKEUP WICPEND FCLK 1 NVIC drives WICLOAD before entering deep sleep 2 Core enters deep sleep The signals below demonstrate the core power down sequence 3 PMU isolates core power domain 4 PMU drives core state retention 5 PMU powers down core 6 Un masked interrupt arrives 7...

Page 149: ...EPDEEP must not be entered or if it has already been entered that WAKEUP be driven high and the SLEEPDEEP policy revert to non WIC based A debugger must hold this signal high when attached to the system to prevent power isolation during debug The sources and causes of wake up events are implementation defined and the implementation can support any number of signals from two and greater This enable...

Page 150: ...te If the debug logic is included in a powered down domain then nTDOEN needs to be handled carefully It cannot be clamped to 0 because this enables it during power down Either Insert inverters either side of the clamp Ensure that the external system masks nTDOEN when the core is powered down Clamp nTDOEN to 1 during power down ...

Page 151: ...d Access Non Confidential Chapter 8 Nested Vectored Interrupt Controller This chapter describes the Nested Vectored Interrupt Controller NVIC It contains the following sections About the NVIC on page 8 2 NVIC programmer s model on page 8 3 Level versus pulse interrupts on page 8 43 ...

Page 152: ...y interrupt processing and efficient processing of late arriving interrupts The NVIC maintains knowledge of the stacked nested interrupts to enable tail chaining of interrupts You can only fully access the NVIC from privileged mode but you can pend interrupts in user mode if you enable the Configuration Control Register see Configuration Control Register on page 8 26 Any other user mode access cau...

Page 153: ...System control configuration and status Fault reporting 0xE000EF00 0xE000EF0F Software Trigger Exception Register 0xE000EFD0 0xE000EFFF ID space Table 8 1 NVIC registers Name of register Type Address Reset value Page Interrupt Control Type Register Read only 0xE000E004 a page 8 7 Auxiliary Control Register Read write 0xE000E008 0x00000000 page 8 8 SysTick Control and Status Register Read write 0xE...

Page 154: ...0000000 page 8 15 Irq 224 to 239 Set Pending Register Read write 0xE000E21C 0x00000000 page 8 15 Irq 0 to 31 Clear Pending Register Read write 0xE000E280 0x00000000 page 8 15 Irq 224 to 239 Clear Pending Register Read write 0xE000E29C 0x00000000 page 8 15 Irq 0 to 31 Active Bit Register Read only 0xE000E300 0x00000000 page 8 16 Irq 224 to 239 Active Bit Register Read only 0xE000E31C 0x00000000 pag...

Page 155: ...D20 0x00000000 page 8 28 System Handler Control and State Register Read write 0xE000ED24 0x00000000 page 8 29 Configurable Fault Status Registers Read write 0xE000ED28 0x00000000 page 8 32 Hard Fault Status Register Read write 0xE000ED2C 0x00000000 page 8 37 Debug Fault Status Register Read write 0xE000ED30 0x00000000 page 8 38 Mem Manage Address Register Read write 0xE000ED34 Unpredictable page 8...

Page 156: ...register PID6 Read only 0xE000EFD8 0x00 Peripheral identification register PID7 Read only 0xE000EFDC 0x00 Peripheral identification register Bits 7 0 PID0 Read only 0xE000EFE0 0x00 Peripheral identification register Bits 15 8 PID1 Read only 0xE000EFE4 0xB0 Peripheral identification register Bits 23 16 PID2 Read only 0xE000EFE8 0x2B Peripheral identification register Bits 31 24 PID3 Read only 0xE00...

Page 157: ...y Protection Unit and Chapter 10 Core Debug respectively Interrupt Controller Type Register Read the Interrupt Controller Type Register to see the number of interrupt lines that the NVIC supports The register address access type and Reset state are Address 0xE000E004 Access Read only Reset state Depends on the number of interrupts defined in this processor implementation Figure 8 1 shows the bit a...

Page 158: ...Reset state are Address 0xE000E008 Access Read write Reset state 0x00000000 Figure 8 2 shows the bit assignments of the Auxiliary Control Register Figure 8 2 Auxiliary Control Register bit assignments Table 8 2 Interrupt Controller Type Register bit assignments Bits Field Function 31 5 Reserved 4 0 INTLINESNUM Total number of interrupt lines in groups of 32 b00000 0 32a b00001 33 64 b00010 65 96 b...

Page 159: ... Status Register Figure 8 3 SysTick Control and Status Register bit assignments Table 8 3 Auxiliary Control Register bit assignments Bits Field Function 31 3 Reserved 2 DISFOLD Disables IT folding 1 DISDEFWBUF Disables write buffer use during default memory map accesses This causes all bus faults to be precise bus faults but decreases the performance of the processor because the stores to memory h...

Page 160: ...et state are Address 0xE000E014 Access Read write Table 8 4 SysTick Control and Status Register bit assignments Bits Field Function 31 17 Reserved 16 COUNTFLAG Returns 1 if timer counted to 0 since last time this was read Clears on read by application of any part of the SysTick Control and Status Register If read by the debugger using the DAP this bit is cleared on read only if the MasterType bit ...

Page 161: ...ent Value Register Use the SysTick Current Value Register to find the current value in the register The register address access type and Reset state are Address 0xE000E018 Access Read write clear Reset state Unpredictable Figure 8 5 shows the bit assignments of the SysTick Current Value Register Figure 8 5 SysTick Current Value Register bit assignments 31 0 RELOAD Reserved 23 24 Table 8 5 SysTick ...

Page 162: ...alibration Value Register Figure 8 6 SysTick Calibration Value Register bit assignments Table 8 7 describes the bit assignments of the SysTick Calibration Value Register Table 8 6 SysTick Current Value Register bit assignments Bits Field Function 31 24 Reserved 23 0 CURRENT Current value at the time the register is accessed No read modify write protection is provided so change with care This regis...

Page 163: ...t invoking an interrupt Clear an Interrupt Set Enable Register bit by writing a 1 to the corresponding bit in the Interrupt Clear Enable Register see Interrupt Clear Enable Registers on page 8 14 Note Clearing an Interrupt Set Enable Register bit does not affect currently active interrupts It only prevents new activations The register address access type and Reset state are Address 0xE000E100 0xE0...

Page 164: ...0xE000E19C Access Read write Reset state 0x00000000 Table 8 9 describes the field of the Interrupt Clear Enable Register Table 8 8 Interrupt Set Enable Register bit assignments Bits Field Function 31 0 SETENA Interrupt set enable bits For write operation 1 enable interrupt 0 no effect For read operation 1 enable interrupt 0 disable interrupt Writing 0 to a SETENA bit has no effect Reading the bit ...

Page 165: ...e Writing to the Interrupt Set Pending Register has no affect on an interrupt that is already pending or is disabled The register address access type and Reset state are Address 0xE000E200 0xE000E21C Access Read write Reset state 0x00000000 Table 8 10 describes the field of the Interrupt Set Pending Register Interrupt Clear Pending Register Use the Interrupt Clear Pending Register to clear pending...

Page 166: ...mine which interrupts are active Each flag in the register corresponds to one of the 32 interrupts The register address access type and Reset state are Address 0xE000E300 0xE00031C Access Read only Reset state 0x00000000 Table 8 12 describes the field of the Active Bit Register Table 8 11 Interrupt Clear Pending Registers bit assignments Bits Field Function 31 0 CLRPEND Interrupt clear pending bit...

Page 167: ...e byte This means that an application can work even if it does not know how many priorities are possible The register address access type and Reset state are Address 0xE000E400 0xE000E41F Access Read write Reset state 0x00000000 Figure 8 7 shows the bit assignments of Interrupt Priority Registers 0 7 for interrupts 0 31 Figure 8 7 Interrupt Priority Registers 0 31 bit assignments The lower PRI_n b...

Page 168: ...on details of the processor core The register address access type and Reset state are Address 0xE000ED00 Access Read only Reset state 0x412FC230 Figure 8 8 shows the bit assignments of the CPUID Base Register Figure 8 8 CPUID Base Register bit assignments Table 8 14 describes the bit assignments of the CPUID Base Register Table 8 13 Interrupt Priority Registers 0 31 bit assignments Bits Field Func...

Page 169: ...ended exception check the vector number of the active exception The register address access type and Reset state are Address 0xE000ED04 Access Read write or read only Reset state 0x00000000 Figure 8 9 on page 8 20 shows the bit assignments of the Interrupt Control State Register 19 16 Constant Reads as 0xF 15 4 PARTNO Number of processor within family 11 10 b11 Cortex family 9 8 b00 version 7 6 b0...

Page 170: ... State Register bit assignments Bits Field Type Function 31 NMIPENDSET Read write Set pending NMI bit 1 set pending NMI 0 do not set pending NMI NMIPENDSET pends and activates an NMI Because NMI is the highest priority interrupt it takes effect as soon as it registers 30 29 Reserved 28 PENDSVSET Read write Set pending pendSV bit 1 set pending pendSV 0 do not set pending pendSV 27 PENDSVCLR Write o...

Page 171: ...ed 22 ISRPENDING Read only Interrupt pending flag Excludes NMI and Faults 1 interrupt pending 0 interrupt not pending 21 12 VECTPENDING Read only Pending ISR number field VECTPENDING contains the interrupt number of the highest priority pending ISR 11 RETTOBASE Read only This bit is 1 when the set of all active exceptions minus the IPSR_current_exception yields the empty set 10 Reserved 9 Reserved...

Page 172: ...upts the alignment must be on a 64 word boundary because table size is 37 words next power of two is 64 Note Table alignment requirements mean that bits 6 0 of the table offset are always zero TBLBASE and TBLOFF are combined with 7 b0000000 to construct the complete vector table base offset value Application Interrupt and Reset Control Register Use the Application Interrupt and Reset Control Regis...

Page 173: ...nts of the Application Interrupt and Reset Control Register 31 16 15 0 VECTKEY VECTKEYSTAT 1 2 Reserved 14 PRIGROUP Reserved 11 8 10 7 ENDIANESS VECTCLRACTIVE VECTRESET 3 SYSRESETREQ Table 8 17 Application Interrupt and Reset Control Register bit assignments Bits Field Function 31 16 VECTKEY Register key Writing to this register requires 0x5FA in the VECTKEY field Otherwise the write value is igno...

Page 174: ...ROUP value represents a point starting at the left of the Least Significant Bit LSB This is bit 0 of 7 0 The lowest value might not be 0 depending on the number of bits allocated for priorities and implementation choices 7 3 Reserved 2 SYSRESETREQ Causes a signal to be asserted to the outer system that indicates a reset is requested Intended to force a large system reset of all major components ex...

Page 175: ...at VECTRESET and SYSRESETREQ be used exclusively and never both written to 1 at the same time System Control Register Use the System Control Register for power management functions signal to the system when the processor can enter a low power state control how the processor enters and exits low power states The register address access type and Reset state are Address 0xE000ED10 Access Read write R...

Page 176: ...ntrol Register bit assignments Bits Field Function 31 5 Reserved 4 SEVONPEND When enabled this causes WFE to wake up when an interrupt moves from inactive to pended Otherwise WFE only wakes up from an event signal external and SEV instruction generated The event input RXEV is registered even when not waiting for an event and so effects the next WFE 3 Reserved 2 SLEEPDEEP Sleep deep bit 1 indicates...

Page 177: ... to restore it is saved The SP is restored on the associated exception return 0 only 4 byte alignment is guaranteed for the SP used prior to the exception on exception entry 8 BFHFNMIGN When enabled this causes handlers running at priority 1 and 2 Hard Fault NMI and FAULTMASK escalated handlers to ignore Data Bus faults caused by load and store instructions When disabled these bus faults cause a l...

Page 178: ... write Reset state 0x00000000 Figure 8 14 on page 8 29 shows the bit assignments of the System Handler Priority Registers 3 UNALIGN_TRP Trap for unaligned access This enables faulting halting on any unaligned half or full word access Unaligned load store multiples always fault The relevant Usage Fault Status Register bit is UNALIGNED see Usage Fault Status Register on page 8 35 2 Reserved 1 USERSE...

Page 179: ...disabled the fault escalates to a Hard Fault The register address access type and Reset state are Address 0xE000ED24 Access Read write Reset state 0x00000000 Figure 8 15 on page 8 30 shows the bit assignments of the System Handler and State Control Register 31 23 16 15 7 0 PRI_5 PRI_4 PRI_6 24 8 PRI_7 PRI_9 PRI_8 PRI_10 PRI_11 PRI_12 PRI_13 PRI_14 PRI_15 E000ED18 E000ED1C E000ED20 Table 8 20 Syste...

Page 180: ...T USGFAULTACT BUSFAULTACT MEMFAULTACT 13 12 2 4 6 9 19 Reserved MEMFAULTPENDED USGFAULTPENDED Reserved Reserved Reserved Table 8 21 System Handler Control and State Register bit assignments Bits Field Function 31 19 Reserved 18 USGFAULTENA Set to 0 to disable else 1 for enabled 17 BUSFAULTENA Set to 0 to disable else 1 for enabled 16 MEMFAULTENA Set to 0 to disable else 1 for enabled 15 SVCALLPEND...

Page 181: ...g this is to save the current state switch out the stack containing the handler s context load the state of the new thread switch in the new thread s stacks and then return to the thread The active bit of the current handler must never be cleared because the IPSR is not changed to reflect this Only use it to change stacked active handlers As indicated the SVCALLPENDED and BUSFAULTPENDED bits are s...

Page 182: ...ister 0xE000ED29 Bus Fault Status Register 0xE000ED2A Usage Fault Status Register Access Read write one to clear Reset state 0x00000000 Figure 8 16 shows the bit assignments of the Configurable Fault Status Registers Figure 8 16 Configurable Fault Status Registers bit assignments Note Accesses to each individual status register must be aligned to the appropriate address and size Either the whole 3...

Page 183: ...address in MMAR A later arriving fault such as a bus fault can clear a memory manage fault 0 no valid fault address in MMAR If a MemManage fault occurs that is escalated to a Hard Fault because of priority the Hard Fault handler must clear this bit This prevents problems on return to a stacked active MemManage handler whose MMAR value has been overwritten 6 5 Reserved 4 MSTKERR Stacking from excep...

Page 184: ...OL Data access violation flag Attempting to load or store at a location that does not permit the operation sets the DACCVIOL flag The return PC points to the faulting instruction This error loads MMAR with the address of the attempted access 0 IACCVIOL Instruction access violation flag Attempting to fetch an instruction from a location that does not permit execution sets the IACCVIOL flag This occ...

Page 185: ... STKERR Stacking from exception has caused one or more bus faults The SP is still adjusted and the values in the context area on the stack might be incorrect The BFAR is not written 3 UNSTKERR Unstack from exception return has caused one or more bus faults This is chained to the handler so that the original return stack is still present SP is not adjusted from failing return and new save is not pe...

Page 186: ... Table 8 24 Usage Fault Status Register bit assignments Bits Field Function 15 10 Reserved 9 DIVBYZERO When DIV_0_TRP see Configuration Control Register on page 8 26 is enabled and an SDIV or UDIV instruction is used with a divisor of 0 this fault occurs The instruction is executed and the return PC points to it If DIV_0_TRP is not set then the divide returns a quotient of 0 8 UNALIGNED When UNALI...

Page 187: ... 20 shows the bit assignments of the Hard Fault Status Register Figure 8 20 Hard Fault Status Register bit assignments 2 INVPC Attempt to load EXC_RETURN into PC illegally Invalid instruction invalid context invalid value The return PC points to the instruction that tried to set the PC 1 INVSTATE Invalid combination of EPSR and instruction for reasons other than UNDEFINED instruction Return PC poi...

Page 188: ...mits If debug and the monitor are both disabled some of these events are Hard Faults and the DBGEVT bit is set in the Hard Fault status register and some are ignored Table 8 25 Hard Fault Status Register bit assignments Bits Field Function 31 DEBUGEVT This bit is set if there is a fault related to debug This is only possible when halting debug is not enabled For monitor enabled debug it only happe...

Page 189: ...er bit assignments Table 8 26 describes the bit assignments of the Debug Fault Status Register 31 4 3 2 1 0 Reserved EXTERNAL VCATCH DWTTRAP BKPT HALTED 5 Table 8 26 Debug Fault Status Register bit assignments Bits Field Function 31 5 Reserved 4 EXTERNAL External debug request flag 1 EDBGRQ signal asserted 0 EDBGRQ signal not asserted The processor stops on next instruction boundary 3 VCATCH Vecto...

Page 190: ... execution The BKPT flag is set by a BKPT instruction in flash patch code and also by normal code Return PC points to breakpoint containing instruction 0 HALTED Halt request flag 1 halt requested by NVIC including step The processor is halted on the next instruction 0 no halt request Table 8 26 Debug Fault Status Register bit assignments continued Bits Field Function Table 8 27 Memory Manage Fault...

Page 191: ...rocessor and a single cycle high level on an external pin causes the corresponding AFSR bit to become latched as one The bit can only be cleared by writing a one to the corresponding AFSR bit When an AFSR bit is written or latched as one an exception does not occur If you require an exception you must use an interrupt The register address access type and Reset state are Address 0xE000ED3C Access R...

Page 192: ...ister Figure 8 22 Software Trigger Interrupt Register bit assignments Table 8 30 describes the bit assignments of the Software Trigger Interrupt Register Table 8 29 Auxiliary Fault Status Register bit assignments Bits Field Function 31 0 IMPDEF Implementation defined The bits map directly onto the signal assignment to the AUXFAULT inputs See Miscellaneous on page A 4 9 31 0 Reserved INTID 8 Table ...

Page 193: ...icularly useful for FIFO and buffer based devices because it ensures that they drain either by a single ISR or by repeated invocations with no extra work This means that the device holds the signal in assert until the device is empty A pulse interrupt can be reasserted during the ISR so that the interrupt can be pended and active at the same time The application design must ensure that a second pu...

Page 195: ...mory Protection Unit This chapter describes the processor Memory Protection Unit MPU It contains the following sections About the MPU on page 9 2 MPU programmer s model on page 9 3 Interrupts and updating the MPU on page 9 19 MPU access permissions on page 9 13 MPU aborts on page 9 15 Updating an MPU region on page 9 16 ...

Page 196: ...MSAv7 model The MPU provides full support for protection regions overlapping protection regions with ascending region priority 7 highest priority 0 lowest priority access permissions exporting memory attributes to the system MPU mismatches and permission violations invoke the programmable priority MemManage fault handler For more information see Memory Manage Fault Address Register on page 8 40 Yo...

Page 197: ...0xE000ED90 Access Read only Table 9 1 MPU registers Name of register Type Address Reset value Page MPU Type Register Read Only 0xE000ED90 0x00000800 page 9 3 MPU Control Register Read Write 0xE000ED94 0x00000000 page 9 4 MPU Region Number register Read Write 0xE000ED98 page 9 6 MPU Region Base Address register Read Write 0xE000ED9C page 9 7 MPU Region Attribute and Size register s Read Write 0xE00...

Page 198: ...bit is set If the PRIVDEFENA bit is set and no regions are enabled then only privileged code can operate When the MPU is disabled the default address map is used as if no MPU is present When the MPU is enabled only the system partition and vector table loads are always accessible Other areas are accessible based on regions and whether PRIVDEFENA is enabled Reserved 31 24 23 16 15 8 7 1 0 IREGION D...

Page 199: ...orities are only possible when in Hard fault NMI or when FAULTMASK is enabled The HFNMIENA bit enables the MPU when operating with these two priorities The register address access type and Reset state are Address 0xE000ED94 Access Read write Reset state 0x00000000 Figure 9 2 shows the bit assignments of the MPU Control Register Figure 9 2 MPU Control Register bit assignments 31 1 0 Reserved HFNMIE...

Page 200: ...gion that is set up overlays this default map and overrides it If this bit 0 the default memory map is disabled and memory not covered by a region faults When the MPU is enabled and PRIVDEFENA is enabled the default memory map is as described in Chapter 4 Memory Map This applies to memory type Execute Never XN cache and shareable rules However this only applies to privileged mode fetch and data ac...

Page 201: ...r example 0x00010000 or 0x00020000 The region always reads back as the current MPU region number VALID always reads back as 0 Writing with VALID 1 and REGION n changes the region number to n This is a short hand way to write the MPU Region Number Register This register is Unpredictable if accessed other than as a word The register address access type and Reset state are Address 0xE000ED9C Access R...

Page 202: ... sizes are used the subregion disable bits must be programmed as 0 The register address access type and Reset state are Address 0xE000EDA0 Access Read write Reset state Unpredictable Figure 9 5 on page 9 9 shows the bit assignments of the MPU Region Attribute and Size Register 31 0 ADDR REGION 4 3 VALID N Table 9 5 MPU Region Base Address Register bit assignments Bits Field Function 31 N ADDR Regi...

Page 203: ...s E N A Table 9 6 MPU Region Attribute and Size Register bit assignments Bits Field Function 31 29 Reserved 28 XN Instruction access disable bit 1 disable instruction fetches 0 enable instruction fetches 27 Reserved 26 24 AP Data access permission field Value Privileged permissions User permissions b000 b001 b010 b011 b100 b101 b110 b111 No access Read write Read write Read write Reserved Read onl...

Page 204: ...nto eight equal sized sub regions Sub regions are not supported for region sizes of 128 bytes and less For more information see Sub Regions on page 9 12 7 6 Reserved 5 1 SIZE MPU Protection Region Size Field See Table 9 7 0 ENABLE Region enable bit Table 9 6 MPU Region Attribute and Size Register bit assignments continued Bits Field Function Table 9 7 MPU protection region size field Region Size b...

Page 205: ...se are described in NVIC register descriptions on page 8 7 The aliases access the registers in exactly the same way and they exist to enable the use of sequential writes STM to update between one and four regions This is used when disable change enable is not required b01110 32KB b01111 64KB b10000 128KB b10001 256KB b10010 512KB b10011 1MB b10100 2MB b10101 4MB b10110 8MB b10111 16MB b11000 32MB ...

Page 206: ... Region Attribute and Size Register divide a region into eight equal sized units based on the region size This enables selectively disabling some of the 1 8th sub regions The least significant bit affects the first 1 8th sub region and the most significant bits affects the last 1 8th sub region A disabled sub region enables any other region overlapping that range to be matched instead If no other ...

Page 207: ...Note In Table 9 8 S is the S bit 2 from the MPU Region Attributes and Size Register Table 9 8 TEX C B encoding TEX C B Description Memory type Region shareability b000 0 0 Strongly ordered Strongly ordered Shareable b000 0 1 Shared device Device Shareable b000 1 0 Outer and inner write through No write allocate Normal S b000 1 1 Outer and inner write back No write allocate Normal S b001 0 0 Outer ...

Page 208: ...write and read allocate 10 Write through no write allocate 11 Write back no write allocate Table 9 10 AP encoding AP 2 0 Privileged permissions User permissions Descriptions 000 No access No access All accesses generate a permission fault 001 Read write No access Privileged access only 010 Read write Read only Writes in user mode generate a permission fault 011 Read write Read write Full access 10...

Page 209: ...on Unit ARM DDI 0337G Copyright 2005 2008 ARM Limited All rights reserved 9 15 Unrestricted Access Non Confidential 9 4 MPU aborts For information about MPU aborts see Memory Manage Fault Address Register on page 8 40 ...

Page 210: ...using an STM instruction 9 5 1 Updating an MPU region using CP15 equivalent code Using CP15 equivalent code R1 region number R2 size enable R3 attributes R4 address MOV R0 NVIC_BASE ADD R0 MPU_REG_CTRL STR R1 R0 0 region number STR R4 R0 4 address STRH R2 R0 8 size and enable STRH R3 R0 10 attributes Note If interrupts could pre empt during this period this region could affect them This means that...

Page 211: ...egion number R2 address R3 size attributes in one MOV R0 NVIC_BASE ADD R0 MPU_REG_CTRL STR R1 R0 0 region number STR R2 R0 4 address STR R3 R0 8 size attributes An STM can optimize this R1 region number R2 address R3 size attributes in one MOV R0 NVIC_BASE ADD R0 MPU_REG_CTRL STM R0 R1 R3 region number address size and attributes You can do this in two words for pre packed information This means t...

Page 212: ...t 2005 2008 ARM Limited All rights reserved ARM DDI 0337G Non Confidential Unrestricted Access STM R0 R1 R2 address region number size For information about interrupts and updating the MPU see Interrupts and updating the MPU on page 9 19 ...

Page 213: ... must disable interrupts around each update routine An interrupt can come in that would use the region being updated or would be affected because only the base or size fields had been updated If the new size field is changed but the base is not the base new_size might overlap into an area normally handled by another region In this case the disable modify enable approach is required But for standar...

Page 215: ...Non Confidential Chapter 10 Core Debug This chapter describes how to debug and test the processor It contains the following sections About core debug on page 10 2 Core debug registers on page 10 3 Core debug access example on page 10 12 Using application registers in core debug on page 10 13 ...

Page 216: ...ister The core acknowledges when halted by setting the S_HALT bit of the Debug Halting Control and Status Register The core can be single stepped by halting the core setting the C_STEP bit to 1 and then clearing the C_HALT bit to 0 The core acknowledges completion of the step and re halt by setting the S_HALT bit of the Debug Halting Control and Status Register 10 1 2 Exiting core debug The core c...

Page 217: ...e 10 8 Debug Exception and Monitor Control Register on page 10 8 10 2 1 Debug Halting Control and Status Register The purpose of the Debug Halting Control and Status Register DHCSR is to provide status information about the state of the processor enable core debug halt and step the processor The DHCSR is a 32 bit read write register address is 0xE000EDF0 Note The DHCSR is only reset from a system ...

Page 218: ... be written whenever this register is written Reads back as status bits 25 16 If not written as Key the write operation is ignored and no bits are written into the register 31 26 Reserved RAZ 25 Read S_RESET_ST Indicates that the core has been reset or is now being reset since the last time this bit was read This a sticky bit that clears on read So reading twice and getting 1 then 0 means it was r...

Page 219: ...unning in halted debug Does not affect NMI which is not maskable Must only be modified when the processor is halted S_HALT 1 Also does not affect fault exceptions and SVC caused by execution of the instructions CMASKINTS must be set or cleared before halt is released This means that the writes to set or clear C_MASKINTS and to set or clear C_HALT must be separate 2 Read write C_STEP Steps the core...

Page 220: ...r bit 0 C_DEBUGEN of the Debug Halting Control and Status Register Note Writes to this register in any size other than word are Unpredictable It is acceptable to read in any size and you can use it to avoid or intentionally change a sticky bit 10 2 2 Debug Core Register Selector Register The purpose of the Debug Core Register Selector Register DCRSR is to select the processor register to transfer ...

Page 221: ...redictable PSR registers are fully accessible this way whereas some read as 0 when using MRS instructions All bits can be written but some combinations cause a fault when execution is resumed IT might be written and behaves as though in an IT block Table 10 3 Debug Core Register Selector Register Bits Type Field Function 31 17 Reserved 16 Write REGWnR Write 1 Read 0 15 5 Reserved 4 0 Write REGSEL ...

Page 222: ...When the processor receives a request from the Debug Core Register Selector this register is read or written by the processor using a normal load store unit operation If core register transfers are not being performed software based debug monitors can use this register for communication in non halting debug For example OS RSD and Real View Monitor This enables flags and bits to acknowledge state a...

Page 223: ...ust be set to 1 to enable use of the trace and debug blocks Data Watchpoint and Trace DWT Instrumentation Trace Macrocell ITM Embedded Trace Macrocell ETM Trace Port Interface Unit TPIU This enables control of power usage unless tracing is required The application can enable this for ITM use or use by a debugger Note If no debug or trace components are present in the implementation then it is not ...

Page 224: ...wever two special cases exist when a vector catch has triggered If a fault is taken during vectoring vector read or stack push error the halt occurs on the corresponding fault handler for the vector error or stack push If a late arriving interrupt comes in during vectoring it is not taken That is an implementation that supports the late arrival optimization must suppress it in this case 15 11 Rese...

Page 225: ...rt Vector catching is semi synchronous When a matching event is seen a Halt is requested Because the processor can only halt on an instruction boundary it must wait until the next instruction boundary As a result it stops on the first instruction of the exception handler However two special cases exist when a vector catch has triggered 1 If a fault is taken during a vector read or stack push error...

Page 226: ...rm the following sequence 1 Write 0xA05F0003 to the Debug Halting Control and Status register This enables debug and halts the core 2 Wait for the S_HALT bit of the Debug Halting and Status Register to be set This indicates that the core is halted 3 Write the value that you want to be written to the Debug Core Register Data Register 4 Write the register number that you want to write to into the De...

Page 227: ...gisters the register can change between the read and the write when performing a read modify write operation In some cases the registers enable byte access to alleviate this situation and the debugger must be aware of these issues when the processor is running Table 10 5 shows the application registers and the register bits that are most useful for use in core debug For a complete list of the appl...

Page 229: ...idential Chapter 11 System Debug This chapter describes the processor system debug It contains the following sections About system debug on page 11 2 System debug access on page 11 3 System debug programmer s model on page 11 5 FPB on page 11 6 DWT on page 11 13 ITM on page 11 30 AHB AP on page 11 39 ...

Page 230: ... and system profiling Instrumentation Trace Macrocell ITM for application driven trace source that supports printf style debugging Embedded Trace Macrocell ETM for instruction trace The processor is supported in versions with and without the ETM All the debug components exist on the internal Private Peripheral Bus PPB and can be accessed using privileged code The system debug components are option...

Page 231: ...Note During a system reset the debugger can read all registers within the PPB space It can also write to registers within the PPB space that are only reset by a power on reset The External Private Peripheral Bus Through this bus debug can access ETM A low cost trace macrocell that supports instruction trace only See Chapter 14 Embedded Trace Macrocell for more information Trace Port Interface Unit...

Page 232: ...Non Confidential Unrestricted Access Figure 11 1 System debug access block diagram CM3Core SW SWJ DP AHB AP Data DCode interface System interface Bridge NVIC ETM DWT FPB ITM MPU TPIU ROM table Internal Private Peripheral Bus PPB External Private Peripheral Bus PPB Bus Matrix Trace port ...

Page 233: ...ribes the debug registers for all the system debug components It contains FPB on page 11 6 DWT on page 11 13 ITM on page 11 30 AHB AP on page 11 39 Note For a description of the Core debug registers see Core debug registers on page 10 3 For a description of the SWJ DP and SW DP registers see Chapter 13 Debug Port For a description of the TPIU see Chapter 17 Trace Port Interface Unit ...

Page 234: ... comparator that matched or is remapped to a BKPT instruction if that feature is enabled The comparison happens dynamically but the result of the comparison occurs too late to stop the original instruction fetch or literal load taking place from the Code space The processor ignores this transaction however and only the remapped transaction is used If an MPU is present the MPU lookups are performed...

Page 235: ...age 11 11 FP_COMP2 Read write 0xE0002010 See Flash Patch Comparator Registers on page 11 11 FP_COMP3 Read write 0xE0002014 See Flash Patch Comparator Registers on page 11 11 FP_COMP4 Read write 0xE0002018 See Flash Patch Comparator Registers on page 11 11 FP_COMP5 Read write 0xE000201C See Flash Patch Comparator Registers on page 11 11 FP_COMP6 Read write 0xE0002020 See Flash Patch Comparator Regi...

Page 236: ...only 0xE0002FF8 Value 0x05 CID3 Read only 0xE0002FFC Value 0xB1 Table 11 1 FPB register summary continued Name Type Address Description 31 3 2 1 0 Reserved 12 4 7 8 NUM_LIT NUM_CODE1 ENABLE 11 14 13 NUM_CODE2 KEY Reserved Table 11 2 Flash Patch Control Register bit assignments Bits Field Function 31 15 Reserved Read As Zero Write Ignored 14 12 NUM_CODE2 Number of full banks of code comparators six...

Page 237: ...ires the remapped access to system space REMAP is the 24 bit 8 word aligned remap address 7 4 NUM_CODE1 Number of code slots field This read only field contains either b0000 to indicate that there are no code slots b0010 to indicate that there are two code slots or b0110 to indicate that there are six code slots 3 2 Reserved 1 KEY Key field To write to the Flash Patch Control Register you must wri...

Page 238: ...004 Access Read write Reset state This register is not reset Figure 11 3 shows the bit assignments of the Flash Patch Remap Register Figure 11 3 Flash Patch Remap Register bit assignments Table 11 3 COMP mapping COMP 2 0 Comparator Description 000 FP_COMP0 Instruction comparator 001 FP_COMP1 Instruction comparator 010 FP_COMP2 Instruction comparator 011 FP_COMP3 Instruction comparator 100 FP_COMP4...

Page 239: ...00C 0xE0002010 0xE0002014 0xE0002018 0xE000201C 0xE0002020 0xE0002024 Reset state Bit 0 ENABLE is reset to 1 b0 Figure 11 4 shows the bit assignments of the Flash Patch Comparator Registers Figure 11 4 Flash Patch Comparator Registers bit assignments Table 11 5 on page 11 12 describes the bit assignments of the Flash Patch Comparator Registers Table 11 4 Flash Patch Remap Register bit assignments ...

Page 240: ...BKPT on upper halfword lower is unaffected b11 set BKPT on both lower and upper halfwords Settings other than b00 are only valid for instruction comparators Literal comparators ignore non b00 settings Address remapping only takes place for the b00 setting 29 Reserved 28 2 COMP Comparison address 1 Reserved 0 ENABLE Compare and remap enable for Flash Patch Comparator Register n 1 Flash Patch Compar...

Page 241: ...he DWT to contain only one comparator that can be used as a watchpoint or as a trigger If only one comparator is present then data matching is not supported The DWT contains counters for clock cycles CYCCNT folded instructions Load Store Unit LSU operations sleep cycles CPI all instruction cycles except for the first cycle interrupt overhead Note An event is emitted each time a counter overflows Y...

Page 242: ...e 11 24 DWT_COMP0 Read write 0xE0001020 See DWT Comparator Registers on page 11 24 DWT_MASK0 Read write 0xE0001024 See DWT Mask Registers 0 3 on page 11 25 DWT_FUNCTION0 Read write 0xE0001028 0x00000000 See DWT Function Registers 0 3 on page 11 25 DWT_COMP1 Read write 0xE0001030 See DWT Comparator Registers on page 11 24 DWT_MASK1 Read write 0xE0001034 See DWT Mask Registers 0 3 on page 11 25 DWT_...

Page 243: ...00000 if one comparator for watchpoints and not triggers is present 0x00000000 if DWT is not present Figure 11 5 on page 11 16 shows the bit assignments of the DWT Control Register PID6 Read only 0xE0001FD8 0x00 Value 0x00 PID7 Read only 0xE0001FDC 0x00 Value 0x00 PID0 Read only 0xE0001FE0 0x02 Value 0x02 PID1 Read only 0xE0001FE4 0xB0 Value 0xB0 PID2 Read only 0xE0001FE8 0x2B Value 0x2B PID3 Read...

Page 244: ...on 31 28 NUMCOMP Number of comparators field This read only field contains the number of comparators present Valid values are b0100 b0001 or b0000 27 NOTRCPKT When set trace sampling and exception tracing are not supported 26 NOEXTTRIG When set no CMPMATCH N support 25 NOCYCCNT When set DWT_CYCCNT is not supported 24 NOPRFCNT When set DWT_FOLDCNT DWT_LSUCNT DWT_SLEEPCNT DWT_EXCCNT and DWT_CPICNT a...

Page 245: ...ount events disabled Reset clears the LSUEVTENA bit 19 SLEEPEVTENA Enables Sleep count event Emits an event when DWT_SLEEPCNT overflows every 256 cycles that the processor is sleeping 1 Sleep count events enabled 0 Sleep count events disabled Reset clears the SLEEPEVTENA bit 18 EXCEVTENA Enables Interrupt overhead event Emits an event when DWT_EXCCNT overflows every 256 cycles of interrupt overhea...

Page 246: ...p CYCTAP 1 selects bit 10 to tap When the selected bit in the CYCCNT register changes from 0 to 1 or 1 to 0 it emits into the POSTCNT bits 8 5 post scalar counter That counter then counts down On a bit change when post scalar is 0 it triggers an event for PC sampling or CYCEVTCNT 8 5 POSTCNT Post scalar counter for CYCTAP When the selected tapped bit changes from 0 to 1 or 1 to 0 the post scalar c...

Page 247: ...ite Reset state 0x00000000 Table 11 8 describes the bit assignments of the DWT Current PC Sampler Cycle Count Register This is a free running counter The counter has three functions When PCSAMPLENA is set the PC is sampled and emitted when the selected tapped bit changes value 0 to 1 or 1 to 0 and any post scalar value counts to 0 When CYCEVTENA is set and PCSAMPLENA is clear an event is emitted w...

Page 248: ...gure 11 6 shows the bit assignments of the DWT CPI Count Register Figure 11 6 DWT CPI Count Register bit assignments Table 11 9 describes the bit assignments of the DWT CPI Count Register DWT Exception Overhead Count Register Use the DWT Exception Overhead Count Register to count the total cycles spent in interrupt processing The register address access type and Reset state are Address 0xE000100C ...

Page 249: ...h the processor is sleeping The register address access type and Reset state are Address 0xE0001010 Access Read write Reset state Figure 11 8 shows the bit assignments of the DTW Sleep Count Register Figure 11 8 DWT Sleep Count Register bit assignments Reserved 31 8 7 0 SLEEPCNT Table 11 10 DWT Exception Overhead Count Register bit assignments Bits Field Function 31 8 Reserved 7 0 EXCCNT Current i...

Page 250: ...he DWT LSU Count Register to count the total number of cycles during which the processor is processing an LSU operation beyond the first cycle The register address access type and Reset state are Address 0xE0001014 Access Read write Reset state Figure 11 9 describes the bit assignments of the DWT LSU Count Register Figure 11 9 DWT LSU Count Register bit assignments Table 11 11 DWT Sleep Count Regi...

Page 251: ...es the bit assignments of the DWT Fold Count Register Table 11 12 DWT LSU Count Register bit assignments Bits Field Function 31 8 Reserved 7 0 LSUCNT LSU counter This counts the total number of cycles that the processor is processing an LSU operation The initial execution cost of the instruction is not counted For example an LDR that takes two cycles to complete increments this counter one cycle E...

Page 252: ...scribes the field of the DWT PCSR DWT Comparator Registers Use the DWT Comparator Registers 0 3 to write the values that trigger watchpoint events The register address access type and Reset state are Address 0xE0001020 0xE0001030 0xE0001040 0xE0001050 Access Read write Reset state Table 11 15 describes the field of DWT Comparator Registers 0 3 Table 11 14 DWT Program Counter Sample Register bit as...

Page 253: ...tion of the comparator Each comparator can Match against either the PC or the data address This is controlled by CYCMATCH This function is only available for comparator 0 DWT_COMP0 Perform data value comparisons if associated address comparators have performed an address match This function is only available for comparator 1 DWT_COMP1 31 0 Reserved 4 MASK 3 Table 11 16 DWT Mask Registers 0 3 bit a...

Page 254: ...e bit assignments of DWT Function Registers 0 3 31 1 0 6 5 4 3 2 Reserved CYCMATCH EMITRANGE FUNCTION 7 8 25 24 23 19 20 16 15 12 11 10 9 MATCHED Reserved DATAVADDR1 DATAVADDR0 DATAVSIZE DATAVMATCH LNK1ENA Reserved Reserved Table 11 17 Bit functions of DWT Function Registers 0 3 Bits Field Function 31 25 Reserved 24 MATCHED This bit is set when the comparator matches and indicates that the operati...

Page 255: ...ison If DATAVMATCH is set in DWT_FUNCTION1 the FUNCTION setting for the comparators given by DATAVADDR0 and DATAVADDR1 are overridden and those comparators only provide the address match for the data comparison 7 CYCMATCH Only available in comparator 0 When set this comparator compares against the clock cycle counter 6 Reserved 5 EMITRANGE Emit range field Reserved to permit emitting offset when r...

Page 256: ...0 sample PC and data value through ITM on read or write EMITRANGE 1 emit address offset and data value through ITM on read or write b0100 Watchpoint on PC match b0101 Watchpoint on read b0110 Watchpoint on write b0111 Watchpoint on read or write b1000 ETM trigger on PC match b1001 ETM trigger on read b1010 ETM trigger on write b1011 ETM trigger on read or write b1100 EMITRANGE 0 sample data for re...

Page 257: ...mparators given by DATAVADDR0 and DATAVADDR1 can then only perform address comparator matches for comparator 1 data matches If the data matching functionality is not included during implementation it is not possible to set DATAVADDR0 DATAVADDR1 or DATAVMATCH in DWT_FUNCTION1 This means that the data matching functionality is not available in the implementation Test the availability of data matchin...

Page 258: ...stamps are emitted relative to packets The ITM contains a 21 bit counter to generate the timestamp The Cortex M3 clock or the bitclock rate of the Serial Wire Viewer SWV output clocks the counter 11 6 1 Summary and description of the ITM registers Note TRCENA of the Debug Exception and Monitor Control Register must be enabled before you program or use the ITM see Debug Exception and Monitor Contro...

Page 259: ...l Read write 0xE0000F00 0x00000000 See ITM Integration Mode Control Register on page 11 36 Lock Access Register Write only 0xE0000FB0 0x00000000 See ITM Lock Access Register on page 11 37 Lock Status Register Read only 0xE0000FB4 0x00000003 See ITM Lock Status Register on page 11 37 PID4 Read only 0xE0000FD0 0x00000004 Value 0x04 PID5 Read only 0xE0000FD4 0x00000000 Value 0x00 PID6 Read only 0xE00...

Page 260: ...lled code guarantees stimulus is not lost by polled access to the ITM r0 Value to write to port r1 and r2 Temporary scratch registers MOV r1 0xE0000000 r1 Stimulus port base Retry LDREX r2 r1 Port 4 Load FIFO full status CMP r2 0 Compare with full ITT NE If not full STREXNE r2 r1 Port 4 Try sending value to port CMPNE r2 1 and check for failure BEQ Retry If full or failed then retry ITM Trace Enab...

Page 261: ... to control which stimulus ports are accessible by user code Note You can only write to this register in privileged mode The register address access type and Reset state are Access Read write Address 0xE0000E40 Reset 0x00000000 Figure 11 13 shows the ITM Trace Privilege Register bit assignments Figure 11 13 ITM Trace Privilege Register bit assignments Table 11 21 describes the bit assignments of t...

Page 262: ...ess 0xE0000E80 Reset 0x00000000 Figure 11 14 shows the ITM Control Register bit assignments Figure 11 14 ITM Trace Control Register bit assignments Table 11 22 describes the bit assignments of the ITM Control Register 31 4 3 0 1 2 7 9 8 10 15 16 Reserved SYNCENA TSENA ITMENA TSPrescale DWTENA 24 23 Reserved ATBID 5 SWOENA BUSY 22 Reserved Table 11 22 ITM Trace Control Register bit assignments Bits...

Page 263: ... behavior count on TPIUACTV and TPIUBAUD 3 DWTENA Enables the DWT stimulus 2 SYNCENA Enables sync packets for TPIU 1 TSENA Enables differential timestamps Differential timestamps are emitted when a packet is written to the FIFO with a non zero timestamp counter and when the timestamp counter overflows Timestamps are emitted during idle times after a fixed number of two million cycles This provides...

Page 264: ...er bit assignments Figure 11 16 ITM Integration Read Register bit assignments Table 11 24 describes the bit assignments of the ITM Integration Read Register ITM Integration Mode Control Register Use this register to enable write accesses to the Control Register Table 11 23 ITM Integration Write Register bit assignments Bits Field Function 31 1 Reserved 0 ATVALIDM When the integration mode is set 0...

Page 265: ...6 describes the bit assignments of the ITM Lock Access Register ITM Lock Status Register Use this register to enable write accesses to the Control Register Figure 11 18 on page 11 38 shows the ITM Lock Status Register bit assignments 31 0 1 Reserved INTEGRATION Table 11 25 ITM Integration Mode Control Register bit assignments Bits Field Function 31 1 Reserved 0 INTEGRATION 0 ATVALIDM normal 1 ATVA...

Page 266: ...ibes the bit assignments of the ITM Lock Status Register 31 0 1 Reserved Present 2 3 ByteAcc Access Table 11 27 ITM Lock Status Register bit assignments Bits Field Function 31 3 Reserved 2 ByteAcc You cannot implement 8 bit lock accesses 1 Access Write access to component is blocked All writes are ignored reads are permitted 0 Present Indicates that a lock mechanism exists for this component ...

Page 267: ... do back to back transactions on the bus and so all transactions are non sequential AHB AP can perform unaligned and bit band transactions The Bus Matrix handles these AHB AP transactions are not subject to MPU lookups AHB AP transactions bypass the FPB and so the FPB cannot remap AHB AP transactions SWJ SW DP initiated transaction aborts drive an AHB AP supported sideband signal called HABORT Thi...

Page 268: ...Register on page 11 40 Transfer Address Read write 0x04 See AHB AP Transfer Address Register on page 11 42 Data Read write Read write 0x0C See AHB AP Data Read Write Register on page 11 43 Banked Data 0 Read write 0x10 See AHB AP Banked Data Registers 0 3 on page 11 43 Banked Data 1 Read write 0x14 See AHB AP Banked Data Registers 0 3 on page 11 43 Banked Data 2 Read write 0x18 See AHB AP Banked D...

Page 269: ...not be changed if transaction is outstanding Debugger must first check TransinProg Reset value 0b1 If the FIXHMASTERTYPE input signal is set to 1 then this register has no affect on the master value indicated by the transaction It is always marked as the debugger 28 26 Reserved 0b000 25 Hprot1 User Privilege control HPROT 1 Reset value 0b1 24 Reserved 0b1 23 12 Reserved 0x000 11 8 Mode Mode of ope...

Page 270: ...ng from 0x1000 to 0x1FFC If the start is at 0x14A0 then the counter increments to 0x1FFC wraps to 0x1000 then continues incrementing to 0x149C 0b00 auto increment off 0b01 increment single Single transfer from corresponding byte lane 0b10 increment packed 0b11 reserved No transfer Size of address increment is defined by the Size field 2 0 Reset value 0b00 3 Reserved 2 0 SIZE Size of access field b...

Page 271: ...ite mode data value to write for the current transfer Read mode data value to read for the current transfer No reset value Table 11 32 AHB AP Banked Data Register bit assignments Bits Field Function 31 0 DATA BD0 BD3 provide a mechanism for directly mapping through DAP accesses to AHB transfers without having to rewrite the TAR within a four location boundary so for example BD0 reads write from TA...

Page 272: ...nments Bits Field Function 31 0 Debug ROM address Base address of debug interface 8 31 0 7 28 24 27 23 17 16 15 Reserved 4 3 AP Type AP Variant JEP 106 indentity code Revision Class JEP 106 continuation code Table 11 34 AHB AP ID Register bit assignments Bits Field Function 31 28 Revision This field is zero for the first implementation of an AP design and is updated for each major revision of the ...

Page 273: ...n page 12 2 AMBA 3 compliance on page 12 3 ICode bus interface on page 12 4 DCode bus interface on page 12 6 System interface on page 12 7 Unifying the code buses on page 12 9 External private peripheral interface on page 12 10 Access alignment on page 12 11 Unaligned accesses that cross regions on page 12 12 Bit band accesses on page 12 13 Write buffer on page 12 14 Memory attributes on page 12 1...

Page 274: ...2 6 The System interface Instruction fetches and data and debug accesses to System space 0x20000000 0xDFFFFFFF 0xE0100000 0xFFFFFFFF are performed over this 32 bit AHB Lite bus For more information see System interface on page 12 7 The External Private Peripheral Bus PPB Data and debug accesses to External PPB space 0xE0040000 0xE00FFFFF are performed over this 32 bit Advanced Peripheral Bus APB A...

Page 275: ...SY transfer undefined length burst the master is permitted to change from BUSY to any other transfer type The processor does not match the given definition because it might change the access type from SEQ or NONSEQ to IDLE during a waited transfer In effect this cancels the outstanding transfer that has not yet occurred because the previous access is wait stated and awaiting completion This enable...

Page 276: ...Instruction fetches 32 bit instruction fetch 31 16 32 bit instruction fetch 15 0 Description Thumb16 15 0 Thumb16 15 0 All Thumb instructions are halfword aligned in memory so two 16 bit Thumb instructions are fetched at a time For sequential code an instruction fetch is performed every second cycle Instruction fetches can be performed on back to back cycles if there is an interrupt or a branch Th...

Page 277: ...actions are performed as non sequentials 12 3 1 Branch status signal A branch status signal BRCHSTAT is exported on the Embedded Trace Macrocell ETM interface that indicates if there are any branches in the pipeline A prefetcher for example can use this to prevent prefetching if a branch is about to be fetched For more information about the branch status signal see Chapter 15 Embedded Trace Macroc...

Page 278: ...ug access until the unaligned access has completed See Access alignment on page 12 11 for a description of unaligned accesses Note It is strongly recommended that any external arbitration between the ICode and DCode AHB bus interfaces ensures that DCode has a higher priority than ICode 12 4 1 Exclusives The DCode bus supports exclusive accesses This is carried out using two sideband signals EXREQD...

Page 279: ...eted For a description of unaligned accesses see Access alignment on page 12 11 12 5 2 Bit band accesses Accesses to the bit band alias region are converted into accesses to the bit band region Bit band writes take two cycles they are converted into read modify write operations and so bit band write accesses stall any subsequent accesses until the bit band access has completed For a description of...

Page 280: ...ge 12 15 12 5 6 Pipelined instruction fetches To provide a clean timing interface on the System bus instruction and vector fetch requests to this bus are registered This results in an additional cycle of latency because instructions fetched from the System bus take two cycles This also means that back to back instruction fetches from the System bus are not possible Note Instruction fetch requests ...

Page 281: ...ive simultaneously in corresponding single cycle address phases then only HTRANSD is asserted The ICode transaction is waited internal to the processor In other words the external ICode bus is forced into an idle state The two HTRANS signals are therefore guaranteed never to be simultaneously active which permits the bus multiplexer to be a very simple device Note DNOTITRANS is a static input that...

Page 282: ...sses are waited until core accesses have completed when there are simultaneous core and debug access to this bus Only the address bits necessary to decode the External PPB space are supported on this interface These address bits are bits 19 2 of PADDR PADDR31 is driven as a sideband signal on this bus When the signal is HIGH it indicates that the AHB AP debug is the requesting master When the sign...

Page 283: ... access it is converted into two or three aligned accesses Note Unaligned accesses that cross into the bit band alias region are not treated as bit band requests and the access is not remapped to the bit band region Instead they are treated as a halfword or byte access to the bit band alias region Table 12 2 Bus mapper unaligned accesses Unaligned access Aligned access Cycle 1 Cycle 2 Cycle 3 Size...

Page 284: ...B space do not wrap within System space For example an unaligned halfword access to the last byte of System space 0xDFFFFFFF is converted by the System interface into a byte access to 0xDFFFFFFF followed by a byte access to 0xE0000000 0xE0000000 is not a valid address on the System bus System accesses that cross into Code space do not wrap within System space For example an unaligned halfword acce...

Page 285: ... the bit band region For reads it extracts the requested bit from the read byte and returns this in the Least Significant Bit LSB of the read data returned to the core For writes it converts the write to an atomic read modify write operation For more information about bit banding see Bit banding on page 4 5 Note The Cortex M3 core does not stall during bit band operations unless it attempts to acc...

Page 286: ...er is full subsequent accesses to the bus stall until the write buffer has drained The write buffer is only used if the bus waits the data phase of the buffered store otherwise the transaction completes on the bus DMB and DSB instructions wait for the write buffer to drain before completing If an interrupt comes in while DMB DSB is waiting for the write buffer to drain the opcode after the DMB DSB...

Page 287: ...e System bus by the addition of a sideband bus MEMATTR Table 12 3 shows the relationship between MEMATTR 0 and HPROT 3 2 Table 12 3 Memory attributes MEMATTR 0 HPROT 3 HPROT 2 Description 0 0 0 Strongly ordered 0 0 1 Device 0 1 0 L1 cacheable L2 not cacheable 1 0 0 Invalid 1 0 1 Invalid 1 1 0 Cache WT allocate on read 0 1 1 Cache WB allocate on read and write 1 1 1 Cache WB allocate on read ...

Page 288: ...resented relatively early in the cycle and they are generated from registers with a small amount of combinatorial logic after the register Requests on this bus have more slack than those presented on the ICODE bus Write data HWDATAD is presented directly from the ALU and is valid approximately 50 into the clock cycle Read data HRDATAD and read response HRESPD are presented directly to the processo...

Page 289: ...0337G Copyright 2005 2008 ARM Limited All rights reserved 13 1 Unrestricted Access Non Confidential Chapter 13 Debug Port This chapter describes the processor Debug Port DP It contains About the DP on page 13 2 ...

Page 290: ... permit pin sharing of JTAG TDO and JTAG TDI when they are not being used for JTAG debug access When used together with a Cortex M3 TPIU there are different options for the connection of Serial Wire Output SWO see Serial wire output connection on page 17 21 The two DP implementations provide different mechanisms for debug access to the processor Your implementation must contain only one of these c...

Page 291: ...ial Chapter 14 Embedded Trace Macrocell This chapter describes the Embedded Trace Macrocell ETM It contains the following sections About the ETM on page 14 2 Data tracing on page 14 7 ETM resources on page 14 8 Trace output on page 14 11 ETM architecture on page 14 12 ETM programmer s model on page 14 16 ...

Page 292: ...ug component that enables reconstruction of program execution The ETM is designed to be a high speed low power debug tool that only supports instruction trace This ensures that area is minimized and that gate count is reduced 14 1 1 ETM block diagram Figure 14 1 on page 14 3 shows a block diagram of the ETM and shows how the ETM interfaces to the Trace Port Interface Unit TPIU ...

Page 293: ...n page 14 4 Miscellaneous configuration inputs See Table 14 2 on page 14 4 Trace port signals See Table 14 2 on page 14 4 Other signals See Table 14 4 on page 14 5 Clocks and resets See Table 14 5 on page 14 6 CM3Trigger CM3 EtmResCntrl CM3 EtmTrigEvt CM3 EtmTrcEn CM3Trace CM3Etm Control CM3Etm FifoPeek CM3Etm Fifo CM3Etm APBIf CM3Etm TraceOut CPU I F APB I F CM3ETM TPIU Formatter TPIU FIFO TPIU O...

Page 294: ...NCH Input ETMFLUSH PC modified before next instruction Input ETMISTALL Indicates that the last instruction signalled by the core has not yet entered execute Input ETMFINDBR PC modified by an indirect operation ETMFLUSH Input ETMINTSTAT 2 0 Exception entry and exit Input ETMINTNUM 8 0 Exception type ETMINTSTAT Input ETMCANCEL Exception is a canceling exception ETMINTSTAT Input COREHALT Core is halt...

Page 295: ...t FCLK Table 14 2 Miscellaneous configuration inputs continued Name Description Direction Clock domain Table 14 3 Trace port signals Name Description Direction Clock domain ATDATAM 7 0 Eight bit trace data Output FCLK ATVALIDM ATDATA is valid Output FCLK ATIDM 6 0 Trace Source ID Output FCLK ATREADYM Indicates that the Trace Port is able to accept the Data on ATDATA Input FCLK AFREADYM Indicates t...

Page 296: ...ame FCLK as Cortex M3 Input PORRESETn Power on reset for the HCLK domain Must not be the same as core HCLK reset SYSRESETn Input Table 14 6 APB interface signals Name Description Direction Clock domain PSEL APB device select Input FCLK PENABLE APB control signal Input FCLK PADDR 11 2 APB Address Bus Input FCLK PWRITE APB Transfer direction Read Write Input FCLK PWDATA 31 0 APB Write Data Bus Input...

Page 297: ... instruction trace with a low pin count data trace is not included in the ETM This considerably reduces gate count for the ETM because the triggering resources are simplified When the ETM is implemented in the processor the two trace sources ITM and ETM both feed into the TPIU where they are combined and usually output over the trace port DWT is able to provide either focused data trace or global ...

Page 298: ...owing internal comparators counters sequencers Table 14 7 lists the Cortex M3 resources Table 14 7 Cortex M3 resources Feature Present on Cortex M3 ETM Architecture version ETMv3 4 Address comparator pairs 0 Data comparators 0 Context ID comparators 0 MMDs 0 Counters 0 Sequencer No Start stop block Yes Embedded ICE comparators 4 External inputs 2 External outputs 0 Extended external inputs 0 Exten...

Page 299: ...te an ETM match input These inputs are presented to the ETM as Embedded In Circuit Emulator ICE comparator inputs A single DWT resource can trigger an ETM event and also generate instrumentation trace directly from the same event Software access to registers Yes Readable registers Yes FIFO size 24 bytes Minimum port size 8 bits Maximum port size 8 bits Normal port mode Normal half rate clocking 1 ...

Page 300: ...11 13 for more information about the DWT unit External inputs Two external inputs ETMEXTIN 1 0 enable additional on chip IP to generate trigger enable signals for the ETM Start stop block The start stop block controls start stop behavior by using the embedded ICE inputs to the ETM The DWT controls these inputs 14 3 3 FIFO functionality The FIFO size is 24 bytes A FIFOFULL output is provided to ena...

Page 301: ...AFVALID unnecessary The Cortex M3 system is equipped with an optimized TPIU that is designed for use with the ETM and ITM This TPIU does not support additional trace sources However you can add additional trace sources if the TPIU has been replaced with a more complex version and more trace infrastructure Note A trace ID register and output are provided for systems that use multiple trace sources ...

Page 302: ...f the instruction being restarted or resumed 14 5 2 Exception return The ETM explicitly indicates return from an exception in the trace stream This is because exception return functionality is encoded in a data dependent manner and an exception return behaves differently from a simple branch The packet encoding indicates a return from an exception Figure 14 2 shows this Figure 14 2 Return from exc...

Page 303: ... None 0 1 byte exception IRQ1 17 1 1 byte exception IRQ2 18 2 1 byte exception IRQ3 19 3 1 byte exception IRQ4 20 4 1 byte exception IRQ5 21 5 1 byte exception IRQ6 22 6 1 byte exception IRQ7 23 7 1 byte exception IRQ0 16 8 1 byte exception Usage Fault 6 9 1 byte exception NMI 2 10 1 byte exception SVC 11 11 1 byte exception DebugMon 12 12 1 byte exception MemManage 4 13 1 byte exception PendSV 14...

Page 304: ...24 24 2 bytes exception IRQ9 25 25 2 bytes exception IRQ10 26 26 2 bytes exception IRQ239 255 255 Table 14 8 Exception tracing mapping continued Number of bytes Exception ETMINTNUM Traced value Address byte 0 Address byte 1 optional Address byte 2 optional Address byte 3 optional Address byte 4 optional Exception information Byte 0 Exception information Byte 1 optional 0 1 2 3 4 5 6 7 C C C C C C ...

Page 305: ...this field Exception byte 0 sets bit 7 to 1 if a second exception byte follows If there is no exception present and only address bits 6 1 change then a single byte is used If an exception is present then at least two bytes signal the address When turning off trace immediately before entry to an exception handler the ETM remains enabled until the exception is taken This enables it to trace the bran...

Page 306: ...TAG DP 14 6 2 List of ETM registers The ETM registers are listed in Table 14 9 For full details see the ARM Embedded Trace Macrocell Architecture Specification Table 14 9 ETM registers Name Type Address Present Description ETM Control Read write 0xE0041000 Yes For a description see page 14 19 Configuration Code Read only 0xE0041004 Yes For a description see page 14 20 Trigger Event Read write 0xE0...

Page 307: ... No FIFOFULL Region Write only 0xE0041028 No If enabled FifoFull logic is always active FIFOFULL Level Read write 0xE004102C Yes The number of bytes left in the FIFO below which the FIFOFULL signal is asserted to stall the core Bit 7 of the ETM Control Register is used to enable the FIFOFULL output ViewData 0xE0041030 0xE004103C No Address Comparators 0xE0041040 0xE004113C No Counters 0xE0041140 0...

Page 308: ...e default behavior CoreSight Trace ID Read write 0xE0041200 Yes Implemented as normal Values of 0x00 0x70 0x7F are reserved and must not be used when the ETM is active OS Save Restore 0xE0041304 0xE0041308 No OS Save Restore not implemented RAZ ignore writes Power Down Status Register Read only 0xE0041314 Yes For a description see page 14 22 ITMISCIN Read only 0xE0041EE0 Yes Sets 1 0 to EXTIN 1 0 ...

Page 309: ...ode 2 Authentication Status Read only 0xE0041FB8 Yes Implemented as normal Device Type Read only 0xE0040FCC Yes Reset value 0x13 Peripheral ID 4 Read only 0xE0041FD0 Yes 0x04 Peripheral ID 5 Read only 0xE0041FD4 Yes 0x00 Peripheral ID 6 Read only 0xE0041FD8 Yes 0x00 Peripheral ID 7 Read only 0xE0041FDC Yes 0x00 Peripheral ID 0 Read only 0xE0041FE0 Yes 0x24 Peripheral ID 1 Read only 0xE0041FE4 Yes ...

Page 310: ...0000 Bits 22 20 are fixed at 0 and not supplied by the ASIC Bits 18 17 are supplied by the MAXEXTIN 1 0 input bus and read the lower value of MAXEXTIN and the number 2 the number of EXTINs This indicates software accesses supported trace start stop block present no CID comparators FIFOFULL logic is present no external outputs 0 2 external inputs controlled by MAXEXTIN no sequencer no counters no M...

Page 311: ...this bit ETM ID Register The ETM ID Register holds the ETM architecture variant and precisely defines the programmer s model for the ETM Reset value 0x4114F242 This indicates ARM implementor special branch encoding affects bits 7 6 of each byte 32 bit Thumb instruction supported core family is found elsewhere ETMv3 4 implementation revision 2 Configuration Code Extension Register The Configuration...

Page 312: ...power domain not powered up 1 ETM debug power domain powered up Note If the ETM is not powered up the ETM registers are not accessible 14 6 4 ETM Event resources The trace enable event and trigger event are configured using the same mechanism For each event two resources are defined together with a boolean function of those two resources Table 14 10 and Table 14 11 on page 14 23 show these Table 1...

Page 313: ...rt Stop resource b110 0 1 ExtIn 0 1 b110 15 HardWired always True Table 14 12 Input connections Trigger bit Source signal Source device Comments 7 ETMTRIGOUT ETM Recommended if ETM is present 6 ETMTRIGGER 2 DWT Recommended 5 ETMTRIGGER 1 DWT Recommended 4 ETMTRIGGER 0 DWT Recommended 3 ACQCOMP ETB See Full 2 FULL ETB Recommended if an ETB is present If a single ETB is shared between multiple cores...

Page 314: ...ETM to the CTI If required this signal must be ORed with an external debug request input and trigger bit 0 from the CTI 4 ETMEXTIN 0 ETM Compulsory if ETM is present 3 INTISR y NVIC See Full 2 INTISR x NVIC Compulsory Any interrupt can be used 1 User defined 0 EDBGRQ Core Compulsory Table 14 13 Trigger output connections continued Trigger bit Source signal Source device Comments ...

Page 315: ...ss Non Confidential Chapter 15 Embedded Trace Macrocell Interface This chapter describes the Embedded Trace Macrocell ETM interface It contains the following sections About the ETM interface on page 15 2 CPU ETM interface port descriptions on page 15 3 Branch status interface on page 15 6 ...

Page 316: ...t 2005 2008 ARM Limited All rights reserved ARM DDI 0337G Non Confidential Unrestricted Access 15 1 About the ETM interface The ETM interface enables simple connection of an ETM to the processor It provides a channel for instruction trace to the ETM ...

Page 317: ...hat the current opcode is a branch target whose destination the PC contents cannot deduce For example LSU register move or interrupt processing ETMDVALID Output No qualifier Signals that the current data address as seen by the Data Watchpoint and Trace DWT is valid on this cycle ETMICCFAIL Output ETMIVALID Opcode condition code fail or pass Marks if the current opcode has failed or passed its cond...

Page 318: ... this cycle PC advances past the current 16 bit opcode and the IT instruction 16 bits This affects the ETMIA ETMFLUSH Output No qualifier Flush marker of PC event A PC modifying opcode has executed or an interrupt push pop has started The ETM can use this control to complete outstanding packets in preparation for an ETMIBRANCH event ETMFINDBR Output ETMFLUSH Flush is indirect Marks that the PC can...

Page 319: ...d execute If ETMICANCEL is asserted with ETMISTALL it indicates that the stalled instruction did not execute and the previous instruction was cancelled ETMTRIGGER 3 0 Output No qualifier Output trigger from DWT One bit for each of the four DWT comparators ETMTRIGINOTD 3 0 Output No qualifier Output indicates if the ETM is triggered on an instruction or data match Table 15 1 ETM interface ports con...

Page 320: ...es a non sequential fetch to occur at decode time or execute time whether the branch is conditional and whether the branch is forward or backwards Execute time branches might have multicycle BRCHSTAT which is dependent on the stall of the preceding opcode in execute Table 15 2 describes the signal function Table 15 3 on page 15 7 shows the branches that the processor can execute For each type of b...

Page 321: ...e B imm 32 bits Decode BL 32 bits Decode If LR is not being written during decode BLX LR 16 bits Decode If LR is not being written during decode BX LR 16 bits Decode If LR is not being written during decode MOV PC LR 16 bits Decode If LR is not being written during decode ADD PC 32 bits Execute BLX 16 bits Execute If LR is not the source register or if LR is being written during decode BX 16 bits ...

Page 322: ...en decode enable is asserted Speculative fetches might be cancelled during wait states This means that the fetch address might change to a new address while HREADY is low See AMBA 3 compliance on page 12 3 Figure 15 1 and Figure 15 2 on page 15 9 show a conditional branch backwards not taken and taken The branch occurs speculatively in the decode phase of the opcode The branch target is a halfword...

Page 323: ... is a halfword aligned 16 bit opcode Figure 15 3 Conditional branch forwards not taken Figure 15 4 Conditional branch forwards taken 0x1002 ETMIVALID ETMCCFAIL ETMIA BRCHSTAT HTRANSI HADDRI HCLK 0x1000 0001 0000 NONSEQ 0x0FF2 NONSEQ NONSEQ IDLE IDLE NONSEQ 0x0FF4 0x0FF8 0x0FFC 0x0FF0 1000 ETMIVALID ETMCCFAIL ETMIA BRCHSTAT HTRANSI HADDRI HCLK 0x1000 0x1002 0010 0000 NONSEQ Fetch ahead of 0x1004 0x...

Page 324: ...Unconditional branch without pipeline stalls Figure 15 6 Unconditional branch with pipeline stalls Figure 15 7 on page 15 11 and Figure 15 8 on page 15 11 show an unconditional branch in the next opcode The branch occurs in the execute phase of the opcode The branch target is an aligned and unaligned 32 bit ALU opcode ETMIVALID ETMCCFAIL ETMIA BRCHSTAT HTRANSI HADDRI HCLK 0x1000 0x1020 0100 0000 N...

Page 325: ...HTRANSI HADDRI HCLK 0x1000 0101 0000 NONSEQ 0x1008 0x1002 0x4000 NONSEQ NONSEQ NONSEQ 0x4000 0x4004 0x400C NONSEQ 0x4008 ETMIVALID ETMCCFAIL ETMIA BRCHSTAT HTRANSI HADDRI HCLK 0x1000 0101 0000 NONSEQ 0x1002 0x4002 NONSEQ NONSEQ NONSEQ 0x4000 0x4004 0x4010 0x1008 NONSEQ NONSEQ 0x4008 0x400C Table 15 4 Example of an opcode sequence Execute cycle Fetch address Opcode 1 0x1020 ADD r1 1 2 0x1022 LDR r3...

Page 326: ...cess Figure 15 9 on page 15 13 shows the timing sequence for the example opcode sequence in Table 15 4 on page 15 11 9 0x1046 LDR NE r3 r4 r2 10 0x1048 ADD r6 r3 11 0x104A NOP 12 0x104C BX r14 13 0x0FC4 CMP 14 0x0FC6 BEQ Target2 not taken 15 0x0FC8 BX r5 Table 15 4 Example of an opcode sequence continued Execute cycle Fetch address Opcode ...

Page 327: ...ADDRI HTRANSI DEn Decode op Execute op 0x811 0x814 0x823 0x826 Idle NONSEQ 0010 1000 0000 0000 0100 0000 0000 0010 0101 NONSEQ NONSEQ NONSEQ Idle NONSEQ 0000 0x102c 0x1030 0x1040 0x1044 0x1048 0x104C 0x1050 0x1054 ADD CMP BEQ CMP LDR LDR ADD NOP BX ITE LDR BEQ BX CMP LDR ADD CMP BEQ ADD LDR LDR ADD NOP BX CMP BEQ BX CMP 0000 0x810 0x812 0x813 0x820 0x822 0x824 0x825 0x7E2 0x7E3 0x7E4 0xFC4 0xFC8 0...

Page 329: ...n Confidential Chapter 16 AHB Trace Macrocell Interface This chapter describes the Advanced High performance Bus AHB trace macrocell interface It contains the following sections About the AHB trace macrocell interface on page 16 2 CPU AHB trace macrocell interface port descriptions on page 16 3 ...

Page 330: ...acrocell interface The AHB Trace Macrocell HTM interface enables a simple connection of the AHB trace macrocell to the processor It provides a channel for the data trace to the HTM To use the HTM interface the trace level must be set to level 3 before implementation TRCENA must also be set to 1 before you enable the HTM to enable the HTM port to supply trace data ...

Page 331: ...SIZE 1 0 Output Indicates the size of the access Can be 8 16 or 32 bits HTMDHBURST 2 0 Output Output indicates if the transfer is part of a burst HTMDHPROT 3 0 Output Provides information on the access HTMDHWDATA 31 0 Output 32 bit write data bus HTMDHWRITE Output Write not read HTMDHRDATA 31 0 Output Read data bus HTMDHREADY Output When HIGH indicates that a transfer has completed on the bus The ...

Page 333: ... rights reserved 17 1 Chapter 17 Trace Port Interface Unit This chapter describes the Trace Port Interface Unit TPIU It contains the following sections About the TPIU on page 17 2 TPIU registers on page 17 8 Serial wire output connection on page 17 21 ...

Page 334: ...you can replace it with CoreSight components if system requirements demand the additional features of the CoreSight TPIU There are two configurations of the TPIU A configuration that supports ITM debug trace A configuration that supports both ITM and ETM debug trace If the implementation requires no trace support then the TPIU might not be present Note If your Cortex M3 system uses the optional ET...

Page 335: ...M Limited All rights reserved 17 3 Figure 17 1 TPIU block diagram non ETM version ATB Interface Asynchronous FIFO APB Interface Trace Out serializer ITM ATB Slave Port APB Slave Port TRACECLKIN TRACECLK TRACEDATA 3 0 TRACESWO CLK Domain TRACECLKIN Domain Formatter ...

Page 336: ...7 5 Asynchronous FIFO The asynchronous FIFO enables trace data to be driven out at a speed that is not dependent on the speed of the core clock Formatter The formatter inserts source ID signals into the data packet stream so that trace data can be re associated with its trace source The formatter is always active when the TRACEPORT mode is active ATB Interface APB Interface Trace Out serializer ET...

Page 337: ...ng Trace out port Advanced Trace Bus interface on page 17 6 Miscellaneous configuration inputs on page 17 6 APB interface on page 17 7 Trace out port Table 17 1 describes the trace out port signals Table 17 1 Trace out port signals Name Type Description TRACECLKIN Input Decoupled clock from ATB to enable easy control of the trace port speed Typically this is derived from a controllable clock sourc...

Page 338: ...cepted this cycle from trace source 1 ATDATA1S 7 0 Input Trace data input from source 1 ATID1S 6 0 Input Trace source ID for source 1 This must not change dynamically ATVALID2S Input Data from trace source 2 is valid in this cycle ATREADY2 Output If this signal is asserted ATVALID high then the data was accepted this cycle from trace source 2 ATDATA2S 7 0 Input Trace data input from source 2 ATID2...

Page 339: ...tes that the TPIU has data that is in the process of being output TPIUBAUD Output Toggles at baud frequency in TRACECLKIN domain Table 17 3 Miscellaneous configuration inputs continued Name Type Description Table 17 4 APB interface Name Type Description PSEL Input Peripheral select PWRITE Input Peripheral write control PENABLE Input Peripheral transfer enable PADDR 11 2 Input Peripheral address PW...

Page 340: ...sync Clock Prescaler Register Read write 0xE0040010 0x0000 page 17 10 Selected Pin Protocol Register Read write 0xE00400F0 0x01 page 17 11 Formatter and Flush Status Register Read only 0xE0040300 0x08 page 17 11 Formatter and Flush Control Register Read write 0xE0040304 0x102 page 17 12 Formatter Synchronization Counter Register Read only 0xE0040308 0x00 page 17 14 Integration Register TRIGGER Rea...

Page 341: ...actual number of TRACEDATA signals wired to physical pins This is to ensure that tools do not attempt to select a port width that an attached TPA cannot capture The value on MAXPORTSIZE causes bits within the Supported Port Size register that represent wider widths to be clear that is unsupported Device ID register Read only 0xE0040FC8 0xCA0 ETM present 0XCA1 ETM not present page 17 20 PID4 Read o...

Page 342: ...rt Sizes Register because it saves on having to decode the sizes later on in the device and also maintains the format from the other register bank for checking for valid assignments On reset this defaults to the smallest possible port size 1 bit and so reads as 0x00000001 Async Clock Prescaler Register Use the Async Clock Prescaler Register to scale the baud rate of the asynchronous output Figure ...

Page 343: ...t assignments Table 17 7 describes the bit assignments of the Selected Pin Protocol Register Note If this register is changed while trace data is being output data corruption occurs Formatter and Flush Status Register Use the Formatter and Flush Status Register to read the status of TPIU formatter The register address access type and Reset state are Address 0xE0040300 Access Read only Reset state ...

Page 344: ...ter The Formatter and Flush Control Register The register address access type and Reset state are Address 0xE0040304 Access Read write Reset state 0x102 Figure 17 7 on page 17 13 shows the bit assignments of the Formatter and Flush Control Register 31 2 0 Reserved 1 FlInProg 3 FtStopped TCPresent FtNonStop 4 Table 17 8 Formatter and Flush Status Register bit assignments Bits Field Function 31 4 Re...

Page 345: ...FOnFlln Reserved EnFCont EnFTC Table 17 9 Formatter and Flush Control Register bit assignments Bits Field Function 31 14 Reserved 13 StopTrig Stop the formatter after a Trigger Event is observed 12 StopFI Stop the formatter after a flush completes 11 Reserved 10 TrigFI Indicates a trigger on Flush completion 9 TrigEVT Indicate a trigger on a Trigger Event 8 TrigIN Indicate a trigger on TRIGIN bein...

Page 346: ...atter causes momentary data corruption Note If the selected pin protocol register is set to 0x00 TracePort mode the Formatter and Flush Control Register always reads 0x102 because the formatter is automatically enabled If one of the serial wire modes is then selected the register reverts to its previously programmed value Formatter Synchronization Counter Register The global synchronization trigge...

Page 347: ...The register address access type and Reset state are Address 0xE0040EF0 Access Read only Reset state 0x0 Figure 17 8 shows the bit assignments of the Integration Test Register bit assignments Figure 17 8 Integration Test Register ITATBCTR2 bit assignments Table 17 10 describes the bit assignments of the Integration Test Register bit assignments Integration Test Register ITATBCTR0 The register addr...

Page 348: ... Integration Mode Control Register enables topology detection The register address access type and Reset state are Address 0xE0040F00 Access Read write Reset state 0x0 Figure 17 10 shows the bit assignments of the Integration Mode Control Register Figure 17 10 Integration Mode Control Register bit assignments 31 0 Reserved 1 ATVALID1 ATVALID2 Table 17 11 Integration Test Register ITATBCTR0 bit ass...

Page 349: ...Register TRIGGER bit assignments Table 17 13 lists the bit assignments of the Integration Register TRIGGER bit assignments Integration Register FIFO data 0 The register address access type and Reset state are Address 0xE0040EEC Access Read only Table 17 12 Integration Mode Control Register bit assignments Bits Field Function 31 2 Reserved SBZ 1 FIFO test mode Enables FIFO test mode 0 Integration t...

Page 350: ...FO data 1 The register address access type and Reset state are Address 0xE0040EFC Access Read only Reset state 0x0 Figure 17 13 on page 17 19 shows the bit assignments of the Integration register FIFO data 1 FIFO1 data 2 FIFO1 data 1 FIFO1 data 0 31 0 29 27 28 26 24 25 23 16 15 8 7 Write point 1 ATVALID1S Write point 2 ATVALID2S 30 Reserved Table 17 14 Integration register FIFO data 0 bit assignme...

Page 351: ...e and Reset state are Address 0xE0040FA4 Access Read write Reset state 0x0 This register forms one half of the Claim Tag value This location enables individual bits to be cleared write and returns the current Claim Tag value read FIFO2 data 2 FIFO2 data 1 FIFO2 data 0 31 0 29 27 28 26 24 25 23 16 15 8 7 Write point 1 ATVALID1S Write point 2 ATVALID2S 30 Reserved Table 17 15 Integration register FI...

Page 352: ...Read write Reset state 0x0 This register forms one half of the Claim Tag value This location enables individual bits to be set write and returns the number of bits that can be set read Read Each bit is considered separately 0 this claim tag bit is not implemented 1 this claim tag bit is implemented Write Each bit is considered separately 0 no effect 1 set this bit in the claim tag Device ID Regist...

Page 353: ... simplest option but it requires an extra package pin Figure 17 14 shows the dedicated pin option Figure 17 14 Dedicated pin used for TRACESWO 17 3 2 SWO shared with TRACEPORT A pin can be shared between TRACEDATA 0 and TRACESWO Because only one of these two pins can be in use at any one time there is no loss of functionality using this option and this is the preferred option when a dedicated trac...

Page 354: ...nfiguration controls If this option is chosen the Instrumentation Trace is not accessible while the debug port is being used in a JTAG configuration Serial wire debug and SWO can be used together at the same time To implement this option the JTAGNSW output from SWJ DP is used to control the multiplexor Figure 17 16 shows the SWO shared with JTAG TDO option Figure 17 16 SWO shared with JTAG TDO CM3...

Page 355: ...estricted Access Non Confidential Chapter 18 Instruction Timing This chapter describes the instruction timings of the processor It contains the following sections About instruction timing on page 18 2 Processor instruction timings on page 18 3 Load store timings on page 18 7 ...

Page 356: ...each instruction in addition to interactions between instructions It also contains information about factors that influence timings When looking at timings it is important to understand the role that the system architecture plays Every instruction must be fetched and every load store must go out to the system These factors are described along with intended system design and the implications for ti...

Page 357: ...RSH STR STRB and STRH and T variants Load store Multiple 16 1 Nb Pa if PC loaded LDMIA POP PUSH and STMIA Exception generating 16 BKPT stops in debug if debug enabled fault if debug disabled SVC faults to SVCall handler see ARMv7 M architecture specification for details Data operations with immediate 32 1 Pa if PC is destination ADC S ADD S CMN RSB S SBC S SUB S CMP AND S TST BIC S EOR S TEQ ORR S...

Page 358: ...rivilege mode Load store Single 32 2b Pa if PC is destination LDR LDRB LDRSB LDRH LDRSH STR STRB and STRH and T variants PLD and PLI are both hints and so act as a NOP Load store Multiple 32 1 Nb Pa if PC is loaded STM LDM LDRD and STRD Load store Special 32 1 Nb LDREX STREX LDREXB LDREXH STREXB STREXH CLREX These fault if no local monitor is IMP DEF LDREXD and STREXD are not included in this prof...

Page 359: ...ructions in addition to accesses to slower memory A branch hint is emitted to the code bus that permits a slower system to pre load This can reduce the branch target penalty for slower memory but never less than shown here b Generally load store instructions take two cycles for the first access and one cycle for each additional access Stores with immediate offsets take one cycle c UMULL SMULL UMLA...

Page 360: ...ghts reserved ARM DDI 0337G Non Confidential Unrestricted Access W sleep wait B barrier clearance In general each instruction takes one cycle one core clock to start executing as Table 18 1 on page 18 3 shows Additional cycles can be taken because of fetch stalls ...

Page 361: ...g instructions include CMP TST NOP and non taken IT controlled instructions LDR PC any is always a blocking operation This means minimally two cycles for the load and three cycles for the pipeline reload So at least five cycles more if stalled on the load or the fetch LDR Rx PC imm might add a cycle because of contention with the fetch unit TBB and TBH are also blocking operations These are minima...

Page 362: ...alled LDM STM cannot be pipelined with preceding or following instructions However all elements after the first are pipelined together So a three element LDM takes 2 1 1 or 5 cycles when not stalled Similarly an eight element store takes nine cycles when not stalled When interrupted LDM and STM instructions continue from where left off when returned to The continue operation adds one or two cycles...

Page 363: ...RM Limited All rights reserved 19 1 Unrestricted Access Non Confidential Chapter 19 AC Characteristics This chapter gives the timing parameters for the processor It contains the following sections Processor timing parameters on page 19 2 ...

Page 364: ...gnal 19 1 1 Input and output port timing parameters Table 19 1 shows the timing parameters for the miscellaneous input ports Table 19 2 shows the timing parameters for the low power input ports Table 19 1 Miscellaneous input ports timing parameters Input delay Min Input delay Max Signal name Clock uncertainty 10 PORESETn Clock uncertainty 10 SYSRESETn Clock uncertainty 50 BIGEND Clock uncertainty ...

Page 365: ...uncertainty 50 INTISR 239 0 Clock uncertainty 50 INTNMI Clock uncertainty 20 VECTADDR 9 0 Clock uncertainty 20 VECTADDREN Table 19 4 AHB input ports timing parameters Input delay Min Input delay Max Signal name Clock uncertainty 10 DNOTITRANS Clock uncertainty 50 HRDATAI 31 0 Clock uncertainty 50 HREADYI Clock uncertainty 50 HRESPI 1 0 Clock uncertainty 50 HRDATAD 31 0 Clock uncertainty 50 HREADYD...

Page 366: ...k uncertainty 50 PREADY Clock uncertainty 50 PSLVERR Table 19 6 Debug input ports timing parameters Input delay Min Input delay Max Signal name Clock uncertainty 10 nTRST Clock uncertainty 50 SWDITMS Clock uncertainty 50 TDI Clock uncertainty 50 DAPRESETn Clock uncertainty 50 DAPSEL Clock uncertainty 50 DAPEN Clock uncertainty 50 DAPENABLE Clock uncertainty 50 DAPCLKEN Clock uncertainty 50 DAPWRIT...

Page 367: ...y Max Signal name Clock uncertainty 10 SE Clock uncertainty 10 SI Clock uncertainty 10 RSTBYPASS Clock uncertainty 10 CGBYPASS Clock uncertainty 10 WSII Clock uncertainty 10 WSOI Table 19 8 ETM input port timing parameters Input delay Min Input delay Max Signal name Clock uncertainty 30 ETMPWRUP Clock uncertainty 50 ETMFIFOFILL Table 19 9 Miscellaneous output ports timing parameters Output delay M...

Page 368: ...name Clock uncertainty 50 SLEEPING Clock uncertainty 50 SLEEPDEEP Clock uncertainty 50 SLEEPHOLDACKn Clock uncertainty 50 WICLOAD Clock uncertainty 50 WICCLEAR Clock uncertainty 50 WICDSACKn Clock uncertainty 50 WICMASKNMI Clock uncertainty 50 WICMASKMON Clock uncertainty 50 WICMASKISR Clock uncertainty 50 WICMASKRXEV Table 19 11 AHB output ports timing parameters Output delay Min Output delay Max...

Page 369: ... Clock uncertainty 50 HBURSTD 2 0 Clock uncertainty 50 HADDRD 31 0 Clock uncertainty 50 HWDATAD 31 0 Clock uncertainty 50 HWRITED Clock uncertainty 50 HMASTERS 1 0 Clock uncertainty 50 HTRANSS 1 0 Clock uncertainty 50 HSIZES 2 0 Clock uncertainty 50 HPROTS 3 0 Clock uncertainty 50 MEMATTRS 1 0 Clock uncertainty 50 EXREQS Clock uncertainty 50 HBURSTS 2 0 Clock uncertainty 50 HMASTLOCKS Clock uncert...

Page 370: ...uncertainty 50 PSEL Clock uncertainty 50 PENABLE Clock uncertainty 50 PWRITE Clock uncertainty 50 PWDATA 31 0 Table 19 13 Debug interface output ports timing parameters Output delay Min Output delay Max Signal name Clock uncertainty 50 SWV Clock uncertainty 50 TRACECLK Clock uncertainty 50 TRACEDATA 3 0 Clock uncertainty 50 TDO Clock uncertainty 50 SWDO Clock uncertainty 50 nTDOEN Clock uncertaint...

Page 371: ...RIGINOTD 3 0 Clock uncertainty 30 ETMIVALID Clock uncertainty 30 ETMDVALID Clock uncertainty 30 ETMFOLD Clock uncertainty 30 ETMCANCEL Clock uncertainty 30 ETMIA 31 1 Clock uncertainty 30 ETMICCFAIL Clock uncertainty 30 ETMIBRANCH Clock uncertainty 30 ETMIINDBR Clock uncertainty 30 ETMFLUSH Clock uncertainty 30 ETMFINDBR Clock uncertainty 30 ETMINTSTAT 2 0 Clock uncertainty 30 ETMINTNUM 8 0 Clock ...

Page 372: ...T 3 0 Clock uncertainty 50 HTMDHWDATA 31 0 Clock uncertainty 50 HTMDHWRITE Clock uncertainty 50 HTMDHRDATA 31 0 Clock uncertainty 50 HTMDHREADY Clock uncertainty 50 HTMDHRESP 1 0 Table 19 16 Test output ports timing parameters Output delay Min Output delay Max Signal name Clock uncertainty 10 SO Clock uncertainty 10 WSOO Clock uncertainty 10 WSIO Table 19 15 HTM interface output ports timing param...

Page 373: ... on page A 2 Resets on page A 3 Miscellaneous on page A 4 Interrupt interface signals on page A 6 Low power interface on page A 7 ICode interface on page A 8 DCode interface on page A 9 System bus interface on page A 10 Private Peripheral Bus interface on page A 11 ITM interface on page A 12 AHB AP interface on page A 13 ETM interface on page A 14 AHB Trace Macrocell interface on page A 16 Test in...

Page 374: ... rights reserved ARM DDI 0337G Non Confidential Unrestricted Access A 1 Clocks Table A 1 lists the clock signals Table A 1 Clock signals Name Direction Description HCLK Input Main Cortex M3 clock FCLK Input Free running Cortex M3 clock DAPCLK Input AHB AP clock ...

Page 375: ... Table A 2 lists the reset signals Table A 2 Reset signals Name Direction Description PORESETn Input Power on reset Resets entire Cortex M3 system SYSRESETn Input System reset Resets processor non debug portion of NVIC Bus Matrix and MPU Debug components are not reset SYSRESETREQ Output System reset request DAPRESETn Input AHB AP reset ...

Page 376: ...nd does not indicate the secondary priority HALTED Output In halting debug mode HALTED remains asserted while the core is in debug DBGRESTARTED Output Handshake for DBGRESTART TXEV Output Event transmitted as a result of SEV instruction This is a single cycle pulse TRCENA Output Trace Enable This signal reflects the setting of bit 24 of the Debug Exception and Monitor Control Register This signal ...

Page 377: ...ces the processor to not permit ICode and DCode AHB transactions to occur at the same time This permits a simple bus multiplexer to be instantiated externally to the processor AUXFAULT 31 0 Input Auxiliary fault status information from the system IFLUSH Input Reserved Instruction flush must be tied to 0 DBGRESTART Input External restart request Table A 3 Miscellaneous signals continued Name Direct...

Page 378: ...DDI 0337G Non Confidential Unrestricted Access A 4 Interrupt interface Table A 4 lists the signals of the external interrupt interface Table A 4 Interrupt interface signals Name Direction Description INTISR 239 0 Input External interrupt signals INTNMI Input Non maskable interrupt ...

Page 379: ...ndicating which interrupts would cause wakeup WICMASKMON Output WIC Active high signal indicating that debug monitor would cause wakeup WICMASKNMI Output WIC Active high signal indicating that NMI would cause wakeup WICMASKRXEV Output WIC Active high signal indicating that RXEV would cause wakeup WICLOAD Output Causes WIC to be loaded with sensitivity data given by WICMASK WICCLEAR Output Causes W...

Page 380: ...ays indicates cacheable and non bufferable on this bus HPROTI 0 0 indicates instruction fetch HPROTI 0 1 indicates vector fetch MEMATTRI 1 0 Output Memory attributes Always 01 for this bus non shareable allocate BRCHSTAT 3 0 Output Provides hint information on the current or coming AHB fetch requests Conditional opcodes could be a speculation and subsequently discarded 0000 No hint 0001 Conditiona...

Page 381: ...x M3 HPROTD 3 0 Output Provides information on the access Always indicates cacheable and non bufferable on this bus EXREQD Output Exclusive request MEMATTRD 1 0 Output Memory attributes Always 01 for this bus non shareable allocate HMASTERD 1 0 Output Indicates the current DCode bus master 0 Core data side accesses 1 DAP accesses 2 Core instruction side accesses These include vector fetches that a...

Page 382: ...a bus HWRITES Output Write not read HMASTLOCKS Output Indicates a transaction that must be atomic on the bus This is only for bit band writes performed as read modify write EXREQS Output Exclusive request MEMATTRS 1 0 Output Memory attributes Bit 0 Allocate Bit 1 shareable HMASTERS 1 0 Output Indicates the current system bus master 0 Core data side accesses or DAP access with MasterType set to 0 1...

Page 383: ...y the bits that are relevant to the External Private Peripheral Bus are driven PADDR31 Output This signal is driven HIGH when the AHB AP is the requesting master It is driven LOW when DCore is the requesting master PSEL Output Indicates that a data transfer is requested PENABLE Output Strobe to time all accesses Indicates the second cycle of an APB transfer PWDATA 31 0 Output 32 bit write data bus...

Page 384: ...f the ITM interface Table A 10 ITM interface Name Direction Description ATVALID Output ATB valid AFREADY Output ATB flush ATDATA 7 0 Output ATB data ATIDITM 6 0 Output ITM ID for TPIU ATREADY Input ATB ready TPIUACTV Input TPIU active indication signal TPIUBAUD Input Reference for the timestamp counter so that timestamps are at the observable baud rate of the external protocol ...

Page 385: ...rom the DAP decoder to each AP This signal indicates that the slave device is selected and a data transfer is required There is a DAPSEL signal for each slave The signal is not generated by the driving DP The decoder monitors the address bus and asserts the relevant DAPSEL DAPENABLE Input This signal indicates the second and subsequent cycles of a DAP transfer from DP to AHB AP DAPWRITE Input When...

Page 386: ...CH Output Opcode is a branch target ETMIINDBR Output Opcode is an indirect branch target ETMINTSTAT 2 0 Output Interrupt status Marks interrupt status of current cycle 000 no status 001 interrupt entry 010 interrupt exit 011 interrupt return 100 vector fetch and stack push ETMINTSTAT entry return is asserted in the first cycle of the new interrupt context Exit occurs without ETMIVALID ETMINTNUM 8 ...

Page 387: ...advances past the current 16 bit opcode plus the IT instruction 16 bits This is reflected in the ETMIA ETMFIFOFULL Input Driven by the ETM if connected ETMFIFOFULL is asserted when the ETM FIFO is full and causes the processor to stall until the FIFO has drained so ensuring that no trace is lost DSYNC Output Synchronization pulse from DWT Table A 12 ETM interface continued Name Direction Descripti...

Page 388: ...TRANS 1 0 Output Output indicates the type of the current data transfer Can be IDLE NONSEQUENTIAL OR SEQUENTIAL HTMDHSIZE 1 0 Output Indicates the size of the access Can be 8 16 or 32 bits HTMDHBURST 2 0 Output Output indicates if the transfer is part of a burst HTMDHPROT 3 0 Output Provides information on the access HTMDHWDATA 31 0 Output 32 bit write data bus HTMDHWRITE Output Write not read HTM...

Page 389: ...nfidential A 14 Test interface Table A 14 lists the signals of the test interface Table A 14 Test interface Name Direction Description SE Input Scan enable RSTBYPASS Input Reset bypass for scan testing PORESETn is the only reset used during scan testing CGBYPASS Input Architectural clock gate bypass for scan testing ...

Page 390: ...WICSLEEP acknowledgement to PMU WICDSREQn Output Active low request to NVIC to make SLEEPDEEP mode WIC sleep FCLK Input Clock synchronous to NVIC FCLK input nRESET Input Asynchronous active low reset WICDISABLE Input Debugger active signal to disable WIC mode when a debugger is attached WICINT Input Peripherals Active high interrupt debug monitor NMI and or RXEV signals WICMASK Input Active high s...

Page 391: ...e B 5 lists the differences between issue F and issue G Table B 1 Differences between issue E and issue F Change Location Introductory processor information updated About the processor on page 1 2 Processor block diagram updated Figure 1 1 on page 1 5 Introductory information added including TPIU subsection Addition of note to SW SWJ DP subsection ROM table subsection Introductory processor core i...

Page 392: ...nd Reset on page 5 20 Description of SLEEPING and SLEEPDEEP signals updated System power management on page 7 3 Description of extending sleep functionality added Extending sleep on page 7 5 Addition of Auxiliary Control Register Table 8 1 on page 8 3 and NVIC register descriptions on page 8 7 Irq 0 to 31 Priority Register amended to Irq 0 to 3 Priority Register Table 8 1 on page 8 3 Irq 236 to 23...

Page 393: ... the ITM registers on page 11 30 ITM Trace Control Register TSENA field bit function updated Table 11 22 on page 11 34 Addition of note about configuring AHB AP registers to be present or not Summary and description of the AHB AP registers on page 11 39 AHB AP Banked Data Register DATA field reset value removed Table 11 32 on page 11 43 Addition of information about absence of debug functionality ...

Page 394: ...ontrol Register on page 14 19 Description of TraceEnable Control 1 Register updated TraceEnable Control 1 Register on page 14 21 Description ETM ID Register updated to reflect revision 2 ETM ID Register on page 14 21 Subsection describing ETM Event Resources added ETM Event resources on page 14 22 Subsection describing Cross Trigger Interface added Cross trigger interface on page 14 23 Branch stat...

Page 395: ...tegration Register FIFO data 1 Claim tag set register Claim tag clear register Device ID register PID registers CID registers Table B 2 Differences between issue F and issue G Change Location Wake up Interrupt Controller WIC added to Cortex M3 block diagram Figure 1 1 on page 1 5 Section 1 2 and section 1 3 combined Components hierarchy and implementation on page 1 4 New subsection added to list c...

Page 396: ...f Irq 224 to 239 Priority Register changed to 0xE000E4EC Table 8 1 on page 8 3 Enhanced description of function of C_MASKINTS field Table 10 2 on page 10 4 Settings for DWT Function Registers updated Table 11 18 on page 11 28 Minor change to timing information of ETMIA Figure 15 4 on page 15 9 Change to timing information for ETMIVALID Figure 15 7 on page 15 11 SLEEPHOLDREQn removed from table of ...

Page 397: ...e signals on page A 7 New section added to describe the WIC interface signals WIC interface signals on page A 18 SLEEPHOLDACKn removed from table of miscellaneous signals Table A 3 on page A 4 Asserted changed to de asserted in the description of SLEEPHOLDREQn in table of low power interface signals Table A 5 on page A 7 FIXMASTERTPYE added to list of AHB AP interface signals Table A 11 on page A ...

Page 399: ... data memory See also Data Abort External Abort and Prefetch Abort Addressing modes Various mechanisms shared by many different instructions for generating values used by the instructions Advanced High performance Bus AHB A bus protocol with a fixed pipeline between address control and data phases It only supports a subset of the functionality provided by the AMBA AXI protocol The full AMBA AHB pr...

Page 400: ...nt of the DAP that provides an AHB interface to a SoC AHB AP See AHB Access Port AHB Lite A subset of the full AMBA AHB protocol specification It provides all of the basic functions required by the majority of AMBA AHB slave and master designs particularly when used with a multi layer AMBA interconnect In most cases the extra facilities provided by a full AMBA AHB interface are implemented more ef...

Page 401: ...ace Bus ATB bridge A synchronous ATB bridge provides a register slice to facilitate timing closure through the addition of a pipeline stage It also provides a unidirectional link between two synchronous ATB domains An asynchronous ATB bridge provides a unidirectional link between two ATB domains with asynchronous clocks It is intended to support connection of components with ATB ports residing in ...

Page 402: ...nected between TDI and TDO through which test data is shifted Processors can contain several shift registers to enable you to access selected parts of the device Branch folding Branch folding is a technique where the branch instruction is completely removed from the instruction stream presented to the execution pipeline Breakpoint A breakpoint is a mechanism provided by debuggers to identify an in...

Page 403: ...ruction CPI Cold reset Also known as power on reset See also Warm reset Context The environment that each process operates in for a multitasking operating system See also Fast context switch Core A core is that part of a processor that contains the ALU the datapath the general purpose registers the Program Counter and the instruction decode and control circuitry Core reset See Warm reset CoreSight...

Page 404: ...ace Macrocell Exception An error or event which can cause the processor to suspend the currently executing instruction stream and execute a specific exception handler or interrupt service routine The exception could be an external interrupt or NMI or it could be a fault or error event that is considered serious enough to require that program execution is interrupted Examples include attempting to ...

Page 405: ...mented by individual implementations Used when there are a number of implementation options available and the option chosen does not affect software compatibility Instruction cycle count The number of cycles for which an instruction occupies the Execute stage of the pipeline Instrumentation trace A component for debugging real time systems through a simple memory mapped trace interface providing p...

Page 406: ...he least significant byte within the halfword at that address See also Big endian memory Load store architecture A processor architecture where data processing operations only operate on register contents not directly on memory contents Load Store Unit LSU The part of a processor that handles load and store transfers LSU See Load Store Unit Macrocell A complex logic block with a defined interface ...

Page 407: ...troller Penalty The number of cycles in which no useful Execute stage pipeline activity can occur because an instruction flow is different from that assumed or predicted PFU See Prefetch Unit PMU See Power Management Unit Power Management Unit PMU Provides the processor with power management capability Power on reset See Cold reset PPB See Private Peripheral Bus Prefetching In pipelined processors...

Page 408: ...One SBZ See Should Be Zero SBZP See Should Be Zero or Preserved Scan chain A scan chain is made up of serially connected devices that implement boundary scan technology using a standard JTAG TAP interface Each device contains at least one TAP controller containing shift registers that form the chain connected between TDI and TDO through which test data is shifted Processors can contain several shi...

Page 409: ...ruction A halfword that specifies an operation for an ARM processor in Thumb state to perform Thumb instructions must be halfword aligned Thumb state A processor that is executing Thumb 16 bit halfword aligned instructions is operating in Thumb state TPA See Trace Port Analyzer TPIU See Trace Port Interface Unit Trace Port Interface Unit TPIU Drains trace data and acts as a bridge between the on c...

Page 410: ...hing between little endian and big endian operation in such a way that the byte with address A in one endianness has address A EOR 3 in the other endianness As a result each aligned word of memory always consists of the same four bytes of memory in the same order regardless of endianness The change of endianness occurs because of the change to the byte addresses not because the bytes are rearrange...

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