Chapter 3 Memory Mapping Control (S12ZMMCV1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
120
Freescale Semiconductor
3.3.2.2
Error Code Register (MMCECH, MMCECL)
Figure 3-5. Error Code Register (MMCEC)
Read: Anytime
Write: Write of 0xFFFF to MMCECH:MMCECL resets both registers to 0x0000
Table 3-5. MMCECH and MMCECL Field Descriptions
Address: 0x0080 (MMCECH)
7
6
5
4
3
2
1
0
R
ITR[3:0]
TGT[3:0]
W
Reset
0
0
0
0
0
0
0
0
Address: 0x0081 (MMCECL)
7
6
5
4
3
2
1
0
R
ACC[3:0]
ERR[3:0]
W
Reset
0
0
0
0
0
0
0
0
Field
Description
7-4
(MMCECH)
ITR[3:0]
Initiator Field
— The ITR[3:0] bits capture the initiator which caused the access violation. The initiator is
captured in form of a 4 bit value which is assigned as follows:
0:
none (no error condition detected)
1:
S12ZCPU
2:
reserved
3:
ADC
4-15: reserved
3-0
(MMCECH)
TGT[3:0]
Target Field
— The TGT[3:0] bits capture the target of the faulty access. The target is captured in form of a
4 bit value which is assigned as follows:
0:
none
1:
register space
2:
RAM
3:
EEPROM
4:
program flash
5:
IFR
6-15: reserved
