Chapter 5 Background Debug Controller (S12ZBDCV2)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
166
Freescale Semiconductor
WRITE_MEM.B{_WS}, WRITE_MEM.W{_WS}, and WRITE_MEM.L{_WS} commands. If enabled
an ACK pulse is generated after the internal write access has been completed or aborted.
The hardware forces low-order address bits to zero longword accesses to ensure these accesses are on 0-
modulo-size alignments. Byte alignment details are described in
”.
5.4.4.17
WRITE_Rn
If the device is in active BDM, this command writes the 32-bit operand to the selected CPU general-
purpose register. See
for the CRN details. Accesses to CPU registers are always 32-bits
wide, regardless of implemented register width. If enabled an ACK pulse is generated after the internal
write access has been completed or aborted.
If the device is not in active BDM, this command is rejected as an illegal operation, the ILLCMD bit is set
and no operation is performed.
5.4.4.18
WRITE_BDCCSR
16-bit write to the BDCCSR register. No ACK pulse is generated. Writing to this register can be used to
configure control bits or clear flag bits. Refer to the register bit descriptions.
5.4.4.19
ERASE_FLASH
Mass erase the internal flash. This command can always be issued. On receiving this command twice in
succession, the BDC sets the ERASE bit in BDCCSR and requests a flash mass erase. Any other BDC
Write general-purpose CPU register
Active Background
0x40+CRN Data [31–24] Data [23–16] Data [15–8]
Data [7–0]
host
target
host
target
host
target
host
target
host
target
D
A
C
K
Write BDCCSR
Always Available
0x0D
BDCCSR
Data [15-8]
BDCCSR
Data [7-0]
host
target
D
L
Y
host
target
host
target
Erase FLASH
Always Available
0x95
host
target
D
L
Y
