Chapter 20 ECC Generation module (SRAM_ECCV1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
680
Freescale Semiconductor
20.2.2.5
ECC Debug Data (ECCDDH, ECCDDL)
20.2.2.6
ECC Debug ECC (ECCDE)
Figure 20-7. ECC Debug ECC (ECCDE)
Table 20-7. ECCDE Field Description
Module Base + 0x000C
Access: User read/write
(1)
1. Read: Anytime
Write: Anytime
7
6
5
4
3
2
1
0
R
DDATA[15:8]
W
Reset
0
0
0
0
0
0
0
0
Module Base + 0x000D
Access: User read/write
7
6
5
4
3
2
1
0
R
DDATA[7:0]
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented
Figure 20-6. ECC Debug Data (ECCDDH, ECCDDL)
Table 20-6. ECCDD Register Field Descriptions
Field
Description
DDATA
[23:0]
ECC Debug Raw Data
— This register contains the raw data which will be written into the system memory
during a debug write command or the read data from the debug read command.
Module Base + 0x000E
Access: User read/write
(1)
1. Read: Anytime
Write: Anytime
7
6
5
4
3
2
1
0
R
0
0
DECC[5:0]
W
Reset
0
0
0
0
0
0
0
0
Field
Description
5:0
DECC[5:0]
ECC Debug ECC
— This register contains the raw ECC value which will be written into the system memory
during a debug write command or the ECC read value from the debug read command.
