Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
382
Freescale Semiconductor
10.4.2.14 ADC End Of List Result Information Register (ADCEOLRI)
This register is cleared when bit ADC_SR is set or bit ADC_EN is clear.
Read: Anytime
Write: Never
NOTE
The conversion interrupt EOL_IF occurs and simultaneously the register
ADCEOLRI is updated when the “End Of List” conversion command type
has been processed and related data has been stored to RAM.
Module Base + 0x0010
7
6
5
4
3
2
1
0
R
CSL_EOL
RVL_EOL
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-17. ADC End Of List Result Information Register (ADCEOLRI)
Table 10-18. ADCEOLRI Field Descriptions
Field
Description
7
CSL_EOL
Active CSL When “End Of List” Command Type Executed
— This bit indicates the active (used) CSL when
a “End Of List” command type has been executed and related data has been stored to RAM.
0 CSL_0 active when “End Of List” command type executed.
1 CSL_1 active when “End Of List” command type executed.
6
RVL_EOL
Active RVL When “End Of List” Command Type Executed
— This bit indicates the active (used) RVL when
a “End Of List” command type has been executed and related data has been stored to RAM.
0 RVL_0 active when “End Of List” command type executed.
1 RVL_1 active when “End Of List” command type executed.
