Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
365
NOTE
Each conversion flow control bit (SEQA, RSTA, TRIG, LDOK) must be
controlled by software or internal interface according to the requirements
described in
Section 10.5.3.2.4, “The two conversion flow control Mode
11-10
ACC_CFG[1:0]
ADCFLWCTL Register Access Configuration
— These bits define if the register ADCFLWCTL is controlled
via internal interface only or data bus only or both. See
. for more details.
9
STR_SEQA
Control Of Conversion Result Storage and RSTAR_EIF flag setting at Sequence Abort or Restart Event
— This bit controls conversion result storage and RSTAR_EIF flag setting when a Sequence Abort Event or
Restart Event occurs as follows:
If STR_SEQA = 1’b0 and if a:
• Sequence Abort Event or Restart Event is issued during a conversion the data of this conversion is not stored
and the respective conversion complete flag is not set
• Restart Event only is issued before the last conversion of a CSL is finished and no Sequence Abort Event is
in process (SEQA clear) causes the RSTA_EIF error flag to be asserted and bit SEQA gets set by hardware
If STR_SEQA = 1’b1 and if a:
• Sequence Abort Event or Restart Event is issued during a conversion the data of this conversion is stored and
the respective conversion complete flag is set and Intermediate Result Information Register is updated.
• Restart Event only occurs during the last conversion of a CSL and no Sequence Abort Event is in process
(SEQA clear) does not set the RSTA_EIF error flag
• Restart Event only is issued before the CSL is finished and no Sequence Abort Event is in process (SEQA
clear) causes the RSTA_EIF error flag to be asserted and bit SEQA gets set by hardware
8
MOD_CFG
(Conversion Flow Control) Mode Configuration
— This bit defines the conversion flow control after a Restart
Event and after execution of the “End Of List” command type:
- Restart Mode
- Trigger Mode
(For more details please see also section
Section 10.5.3.2, “Introduction of the Programmer’s Model
and
following.)
0 “Restart Mode” selected.
1 “Trigger Mode” selected.
Table 10-3. ADCFLWCTL Register Access Configurations
ACC_CFG[1]
ACC_CFG[0]
ADCFLWCTL Access Mode
0
0
None of the access paths is enabled
(default / reset configuration)
0
1
Single Access Mode - Internal Interface
(ADCFLWCTL access via internal interface only)
1
0
Single Access Mode - Data Bus
(ADCFLWCTL access via data bus only)
1
1
Dual Access Mode
(ADCFLWCTL register access via internal interface and data bus)
Table 10-2. ADCCTL_0 Field Descriptions (continued)
Field
Description
