Chapter 3 Memory Mapping Control (S12ZMMCV1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
122
Freescale Semiconductor
Table 3-6. MMCCCRH and MMCCCRL Field Descriptions
3.3.2.4
Captured S12ZCPU Program Counter (MMCPCH, MMCPCM, MMCPCL)
Figure 3-7. Captured S12ZCPU Program Counter (MMCPCH, MMCPCM, MMCPCL)
Read: Anytime
Write: Never
Field
Description
7
(MMCCCRH)
CPUU
S12ZCPU User State Flag
— This bit shows the state of the user/supervisor mode bit in the S12ZCPU’s CCR
at the time the access violation has occurred. The S12ZCPU user state flag is read-only; it will be automatically
updated when the next error condition is flagged through the MMCEC register. This bit is undefined if the error
code registers (MMCECn) are cleared.
6
(MMCCCRL)
CPUX
S12ZCPU X-Interrupt Mask
— This bit shows the state of the X-interrupt mask in the S12ZCPU’s CCR at the
time the access violation has occurred. The S12ZCPU X-interrupt mask is read-only; it will be automatically
updated when the next error condition is flagged through the MMCEC register. This bit is undefined if the error
code registers (MMCECn) are cleared.
4
(MMCCCRL)
CPUI
S12ZCPU I-Interrupt Mask
— This bit shows the state of the I-interrupt mask in the CPU’s CCR at the time the
access violation has occurred. The S12ZCPU I-interrupt mask is read-only; it will be automatically updated
when the next error condition is flagged through the MMCEC register. This bit is undefined if the error code
registers (MMCECn) are cleared.
Address: 0x0085 (MMCPCH)
7
6
5
4
3
2
1
0
R
CPUPC[23:16]
W
Reset
0
0
0
0
0
0
0
0
Address: 0x0086 (MMCPCM)
7
6
5
4
3
2
1
0
R
CPUPC[15:8]
W
Reset
0
0
0
0
0
0
0
0
Address: 0x0087 (MMCPCL)
7
6
5
4
3
2
1
0
R
CPUPC[7:0]
W
Reset
0
0
0
0
0
0
0
0
