Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
419
10.8.9
Triggered Conversion — Single CSL
Applications that require the conversion of one or more groups of different channels in a periodic and
timed manner can make use of a configuration in “Trigger Mode” with a single CSL containing a list of
sequences. This means the CSL consists of several sequences each separated by an “End of Sequence”
command. The last command of the CSL uses the “End Of List” command with wrap to top of CSL and
waiting for a Trigger (CMD_SEL[1:0] =2’b11). Hence after the initial Restart Event each sequence can be
launched via a Trigger Event and repetition of the CSL can be launched via a Trigger after execution of
the “End Of List” command.
Figure 10-42. Conversion Flow Control Diagram — Triggered Conversion (CSL Repetition)
Figure 10-43. Conversion Flow Control Diagram — Triggered Conversion (with Stop Mode)
In case a Low Power Mode is used:
If bit AUT_RSTA is set before Low Power Mode is entered, the conversion continues automatically as
soon as a low power mode (Stop Mode or Wait Mode with bit SWAI set) is exited.
CSL_0
Active
AN3 AN1 AN4 IN5
Initial
Restart
Event
EOS
AN2 AN0 AN4 IN3
EOS
AN3 AN1 AN4
AN6 AN1 IN1
EOL
Trigger
Trigger
Trigger
Sequence_0
Sequence_1
Sequence_0
Sequence_2
Repetition of CSL_0
t
CSL_0
Active
AN3 AN1 AN4 IN5
initial
Restart
Event
EOS
AN21AN0 AN4 IN3
EOS
AN6 AN1
Stop Mode request,
Automatic Sequence Abort
Event
Idle
Stop Mode
entry
Wake-up
Event with
Idle
AUT_RSTA
Active
AN3 AN1 AN4
Abort
Sequence_0
Sequence_1
Trigger
Trigger
EOS
Sequence_0
Sequence_2
AN5 AN2 AN0
Sequence_1
Trigger
Begin from top of current CSL
t
