Chapter 6 S12Z Debug (S12ZDBGV2) Module
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
227
6.4.7.3.1
DBG Breakpoint Priorities And BDC Interfacing
Breakpoint operation is dependent on the state of the S12ZBDC module. BDM cannot be entered from a
breakpoint unless the BDC is enabled (ENBDC bit is set in the BDC). If BDM is already active,
breakpoints are disabled. In addition, while executing a BDC STEP1 command, breakpoints are disabled.
When the DBG breakpoints are mapped to BDM (BDMBP set), then if a breakpoint request, either from
a BDC BACKGROUND command or a DBG event, coincides with an SWI instruction in application
code, (i.e. the DBG requests a breakpoint at the next instruction boundary and the next instruction is an
SWI) then the CPU gives priority to the BDM request over the SWI request.
On returning from BDM, the SWI from user code gets executed. Breakpoint generation control is
summarized in
.
6.5
Application Information
6.5.1
Avoiding Unintended Breakpoint Re-triggering
Returning from an instruction address breakpoint using an RTI or BDC GO command without PC
modification, returns to the instruction that generated the breakpoint. If an active breakpoint or trigger still
exists at that address, this can re-trigger, disarming the DBG. If configured for BDM breakpoints, the user
must apply the BDC STEP1 command to increment the PC past the current instruction.
If configured for SWI breakpoints, the DBG can be re configured in the SWI routine. If a comparator
match occurs at an SWI vector address then a code SWI and DBG breakpoint SWI could occur
simultaneously. In this case the SWI routine is executed twice before returning.
6.5.2
Debugging Through Reset
To debug through reset, the debugger can recognize a reset occurrence and pull the device BKGD pin low.
This forces the device to leave reset in special single chip (SSC) mode, because the BKGD pin is used as
the MODC signal in the reset phase. When the device leaves reset in SSC mode, CPU execution is halted
and the device is in active BDM. Thus the debugger can configure the DBG for tracing and breakpoints
before returning to application code execution. In this way it is possible to analyze the sequence of events
emerging from reset. The recommended handling of the internal reset scenario is as follows:
Table 6-61. Breakpoint Mapping Summary
BRKCPU
BDMBP Bit
(DBGC1[4])
BDC
Enabled
BDM
Active
Breakpoint
Mapping
0
X
X
X
No Breakpoint
1
0
X
0
Breakpoint to SWI
1
0
1
1
No Breakpoint
1
1
0
X
No Breakpoint
1
1
1
0
Breakpoint to BDM
1
1
1
1
No Breakpoint
