Chapter 20 ECC Generation module (SRAM_ECCV1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
681
20.2.2.7
ECC Debug Command (ECCDCMD)
Figure 20-8. ECC Debug Command (ECCDCMD)
Table 20-8. ECCDCMD Field Description
20.3
Functional Description
The bus system allows 1, 2, 3 and 4 byte write access to a 4 byte aligned memory address, but the ECC
value is generated based on an aligned 2 byte data word. Depending on the access type, the access is
separated into different access cycles.
shows the different access types with the expected
number of access cycles and the performed internal operations.
Module Base + 0x000F
Access: User read/write
(1)
1. Read: Anytime
Write: Anytime, in special mode only
7
6
5
4
3
2
1
0
R
ECCDRR
0
0
0
0
0
ECCDW
ECCDR
W
Reset
0
0
0
0
0
0
0
0
Field
Description
7
ECCDRR
ECC Disable Read Repair Function
— Write one to this register bit will disable the automatic single bit ECC
error repair function during read access, see also chapter
0 Automatic single ECC error repair function is enabled
1 Automatic single ECC error repair function is disabled
1
ECCDW
ECC Debug Write Command
— Write one to this register bit will perform a debug write access to the system
memory. During this access the debug data word (DDATA) and the debug ECC value (DECC) will be written to
the system memory address defined by DPTR. If the debug write access is done this bit is cleared. Writing 0 has
no effect
.
It is not possible to set this bit if the previous debug access is ongoing. (ECCDW or ECCDR bit set)
0
ECCDR
ECC Debug Read Command
— Write one to this register bit will perform a debug read access from the system
memory address defined by DPTR. If the debug read access is done this bit is cleared and the raw memory read
data are available in register DDATA and the raw ECC value is available in register DECC. Writing 0 has no
effect. If the ECCDW and ECCDR bit are set at the same time, then only the ECCDW bit is set and the Debug
Write Command is performed. It is not possible to set this bit if the previous debug access is ongoing. (ECCDW
or ECCDR bit set)
Table 20-9. Memory access cycles
Access type
ECC
error
access
cycle
Internal operation
Memory
content
Error indication
2 and 4 byte
aligned write
access
-
1
write to memory
new data
-
