Chapter 20 ECC Generation module (SRAM_ECCV1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
679
20.2.2.4
ECC Debug Pointer Register (ECCDPTRH, ECCDPTRM,
ECCDPTRL)
Module Base + 0x0007
Access: User read/write
(1)
1. Read: Anytime
Write: Anytime
7
6
5
4
3
2
1
0
R
DPTR[23:16]
W
Reset
0
0
0
0
0
0
0
0
Module Base + 0x0008
Access: User read/write
7
6
5
4
3
2
1
0
R
DPTR[15:8]
W
Reset
0
0
0
0
0
0
0
0
Module Base + 0x0009
Access: User read/write
7
6
5
4
3
2
1
0
R
DPTR[7:1]
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented
Figure 20-5. ECC Debug Pointer Register (ECCDPTRH, ECCDPTRM, ECCDPTRL)
Table 20-5. ECCDPTR Register Field Descriptions
Field
Description
DPTR
[23:0]
ECC Debug Pointer
— This register contains the system memory address which will be used for a debug
access. Address bits not relevant for SRAM address space are not writeable, so the SW should read back the
pointer value to make sure the register contains the intended memory address. Anyway it is possible to write
an address value to this register which points outside the system memory. There is no additional monitoring of
the register content, therefore the SW must make sure that the address value points to the system memory
space.
