Chapter 20 ECC Generation module (SRAM_ECCV1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
677
20.2.2
Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register
diagram with an associated figure number. Details of register bit and field functions follow the register
diagrams, in bit order.
20.2.2.1
ECC Status Register (ECCSTAT)
Figure 20-2. ECC Status Register (ECCSTAT)
Table 20-2. ECCSTAT Field Description
20.2.2.2
ECC Interrupt Enable Register (ECCIE)
Figure 20-3. ECC Interrupt Enable Register (ECCIE)
Table 20-3. ECCIE Field Description
Module Base + 0x00000
Access: User read only
(1)
1. Read: Anytime
Write: Never
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
RDY
W
Reset
0
0
0
0
0
0
0
0
Field
Description
0
RDY
ECC Ready
— Shows the status of the ECC module.
0 Internal SRAM initialization is ongoing, access to the SRAM is disabled
1 Internal SRAM initialization is done, access to the SRAM is enabled
Module Base + 0x00001
Access: User read/write
(1)
1. Read: Anytime
Write: Anytime
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
SBEEIE
W
Reset
0
0
0
0
0
0
0
0
Field
Description
0
SBEEIE
Single bit ECC Error Interrupt Enable
— Enables Single ECC Error interrupt.
0 Interrupt request is disabled
1 Interrupt will be requested whenever SBEEIF is set
