Chapter 20 ECC Generation module (SRAM_ECCV1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
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access is always a 2 byte aligned memory access, so that no ECC check is performed and no single or
double bit ECC error indication are activated.
20.3.7.2
ECC Debug Memory Read Access
Writing one to the ECCDR bit performs a debug read access from the memory address defined by register
DPTR. If the ECCDR bit is cleared then the register DDATA contains the uncorrected read data from the
memory. The register DECC contains the ECC value read from the memory. Independent of the ECCDRR
register bit setting, the debug read access will not perform an automatic ECC repair during read access.
During the debug read access no ECC check is performed, so that no single or double bit ECC error
indication are activated.
If the ECCDW and the ECCDR bits are set at the same time, then only the debug write access is performed.
