Chapter 2
Analog Input Timing/Control
DAQ-STC Technical Reference Manual
2-52
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National Instruments Corporation
AI_Delayed_START2
bit: 10
type: Write
in: AI_Mode_3_Register
address: 87
This bit determines when the START2 trigger is used by the AITM:
0: Use START2 trigger immediately.
1: Delay the START2 trigger by synchronizing it to the CONVERT source.
Set this bit to 1 in the master ASIC during master/slave trigger. The slave ASIC can then
synchronize to the same clock as the master by triggering on the START2 signal that is output
from the master.
AI_Delay_START
bit: 14
type: Write
in: AI_Mode_3_Register
address: 87
This bit selects the internal clock that synchronizes the START trigger when START
synchronization is selected:
0: START synchronizes to SI2_SRC (internal CONVERT) or to FSCLK (external
CONVERT).
1: START synchronizes to SC_SRC.
Since the clock SC_SRC is internally delayed relative to SI2_SRC and FSCLK, setting this
bit to 1 provides additional margin for the external START to reach the synchronization
flip-flop, but allows less margin for the output of the synchronization flip-flop to reach the
counter control circuits. You should normally set this bit to 0.
Related bitfields: AI_START_Sync.
AI_Disarm
bit: 13
type: Strobe
in: AI_Command_1_Register
address: 8
Setting this bit to 1 asynchronously disarms the SC, SI, SI2, and DIV counters. This command
should only be used to disarm idle counters. To disarm non-idle counters, use
AI_Software_Reset. This bit is cleared automatically.
Related bitfields: AI_Software_Reset.
AI_DIV_Arm
bit: 8
type: Strobe
in: AI_Command_1_Register
address: 8
This bit arms the DIV counter. The counter remains armed (and the bit remains set) until it is
disarmed, either by hardware or by setting AI_Disarm to 1. Related bitfields:
AI_DIV_Armed_St, AI_Disarm.
