Chapter 3
Analog Output Timing/Control
©
National Instruments Corporation
3-53
DAQ-STC Technical Reference Manual
AO_DMA_PIO_Control
bit: 8
type: Write
in: AO_Personal_Register
address: 78
This bit selects the data interface mode:
0: FIFO data interface mode.
1: Unbuffered data interface mode.
You should set this bit to 0 on a board with an AO data FIFO. Set this bit to 1 on a board
without an AO data FIFO. Refer to section
, for more information on
the data interface modes.
AO_End_On_BC_TC
bit: 15
type: Strobe
in: AO_Command_2_Register
address: 5
Setting this bit to 1 causes the BC, UC, and UI counters to be stopped but not disarmed at the
next BC_TC. You can use this bit to stop waveform generation in the continuous mode so that
the AOTM will end up in a retriggerable state. This action is internally synchronized to the
falling edge of the UC source. This bit is cleared automatically. Related bitfields:
AO_Continuous.
AO_End_On_UC_TC
bit: 14
type: Strobe
in: AO_Command_2_Register
address: 5
Setting this bit to 1 causes the BC, UC, and UI counters to be disarmed at the next UC_TC.
You can use this bit to stop waveform generation in the continuous mode. This action is
internally synchronized to the falling edge of the UC source. This bit is cleared automatically.
Related bitfields: AO_Continuous.
AO_Error_Interrupt_Ack
bit: 13
type: Strobe
in: Interrupt_B_Ack_Register
address: 3
Setting this bit to 1 clears AO_Overrun_St and acknowledges the Error interrupt request (in
either interrupt bank) if the Error interrupt is enabled. This bit is cleared automatically.
Related bitfields: AO_Overrun_St.
AO_Error_Interrupt_Enable
bit: 5
type: Write
in: Interrupt_B_Enable_Register
address: 75
This bit enables the Error interrupt:
0: Disabled.
1: Enabled.
The Error interrupt is generated on the detection of an overrun error condition.
