HOST INTERFACE (HI)
5 - 20
PORT B
MOTOROLA
registers in the HI unnecessary.
5.3.3.1
Programming Model – Host Processor Viewpoint
The HI appears to the host processor as a memory-mapped peripheral occupying eight
bytes in the host processor address space (see Figure 5-12 and Figure 5-13). These reg-
isters can be viewed as one control register (ICR), one status register (ISR), three data
registers (RXH/TXH, RXM/TXM, and RXL/TXL), and two vector registers (IVR and CVR).
The CVR is a special command register that is used by the host processor to issue com-
mands to the DSP. These registers can be accessed only by the host processor; they
can not be accessed by the DSP CPU. Host processors may use standard host proces-
sor instructions (e.g., byte move) and addressing modes to communicate with the HI
registers. The HI registers are addressed so that 8-bit MC6801-type host processors can
use 16-bit load (LDD) and store (STD) instructions for data transfers. The 16-bit
MC68000/MC68010 host processor can address the HI using the special MOVEP
instruction for word (16-bit) or long-word (32-bit) transfers. The 32-bit MC68020 host pro-
cessor can use its dynamic bus sizing feature to address the HI using standard MOVE
word (16-bit), long-word (32-bit) or quad-word (64-bit) instructions. The HREQ and
HACK handshake flags are provided for polled or interrupt-driven data transfers with the
host processor. Because the DSP interrupt response is sufficiently fast, most host micro-
processors can load or store data at their maximum programmed I/O (non-DMA)
instruction rate without testing the handshake flags for each transfer. If the full hand-
shake is not needed, the host processor can treat the DSP as fast memory, and data can
be transferred between the host processor and the DSP at the fastest host processor
data rate. DMA hardware may be used with the handshake flags to transfer data without
host processor intervention.
One of the most innovative features of the host interface is the host command feature.
With this feature, the host processor can issue vectored exception requests to the
DSP56002. The host may select any one of 64 DSP56002 exception routines to be exe-
cuted by writing a vector address register in the HI. This flexibility allows the host
programmer to execute up to 64 preprogrammed functions inside the DSP56002. For
example, host exceptions can allow the host processor to read or write DSP56002 regis-
ters (X, Y, or program memory locations), force exception handlers (e.g., SSI, SCI, IRQA,
IRQB exception routines), and perform control and debugging operations if exception rou-
tines are implemented in the DSP56002 to perform these tasks.
5.3.3.2
Interrupt Control Register (ICR)
The ICR is an 8-bit read/write control register used by the host processor to control the HI
interrupts and flags. ICR cannot be accessed by the DSP CPU. ICR is a read/write regis-
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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