HOST INTERFACE (HI)
5 - 66
PORT B
MOTOROLA
5.3.6.5
Host Port Usage Considerations – Host Side
Synchronization is a common problem when two asynchronous systems are connected,
and careful synchronization is required when reading multi-bit registers that are written by
another asynchronous system. The considerations for proper operation are discussed
below.
1. Unsynchronized Reading of Receive Byte Registers:
When reading receive byte registers, RXH, RXM, or RXL, the host programmer
should use interrupts or poll the RXDF flag which indicates that data is avail-
able. This guarantees that the data in the receive byte registers will be stable.
2. Overwriting Transmit Byte Registers:
The host programmer should not write to the transmit byte registers, TXH, TXM,
or TXL, unless the TXDE bit is set, indicating that the transmit byte registers are
empty. This guarantees that the DSP will read stable data when it reads the
HRX register.
3. Synchronization of Status Bits from DSP to Host:
HC, HREQ, DMA, HF3, HF2, TRDY, TXDE, and RXDF status bits are set or
cleared from inside the HI and read by the host processor. The host can read
these status bits very quickly without regard to the clock rate used by the DSP,
but there is a chance that the state of the bit could be changing during the read
operation. This possible change is generally not a system problem, since the
bit will be read correctly in the next pass of any host polling routine.
However, if the host holds HEN for the minimum assertion time plus x clock
cycles (see “Host Port Usage Considerations” in the DSP56002 Technical Data
Sheet (DSP56002/D) for the minimum number of cycles), the status data is
guaranteed to be stable. The x clock cycles are used to synchronize the HEN
signal and block internal updates of the status bits. There is no other minimum
HEN assertion time relationship to DSP clocks. There is a minimum HEN deas-
sertion time so that the blocking latch can be updated if the host is in a tight
polling loop. This minimum time only applies to reading status bits.
The only potential problem with the host processor’s reading of status bits
would be its reading HF3 and HF2 as an encoded pair. For example, if the DSP
changes HF3 and HF2 from “00” to “11”, there is a small possibility that the host
could read the bits during the transition and receive “01” or “10” instead of “11”.
If the combination of HF3 and HF2 has significance, the host processor could
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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