SYNCHRONOUS SERIAL INTERFACE (SSI)
MOTOROLA
PORT C
6 - 97
6.4.2.3.7
SSISR SSI Transmit Data Register Empty (TDE) Bit 6
This flag is set when the contents of the transmit data register are transferred to the trans-
mit shift register; it is also set for a disabled time slot period in network mode (as if data
were being transmitted after the TSR was written). Thirdly, it can be set by the hardware,
software, SSI individual, or STOP reset. When set, TDE indicates that data should be writ-
ten to the TX or to the time slot register (TSR). TDE is cleared when the DSP writes to the
transmit data register or when the DSP writes to the TSR to disable transmission of the
next time slot. If TIE is set, a DSP transmit data interrupt request will be issued when TDE
is set. The vector of the interrupt will depend on the state of the transmitter underrun bit.
6.4.2.3.8
SSISR SSI Receive Data Register Full (RDF) Bit 7
RDF is set when the contents of the receive shift register are transferred to the receive
data register. RDF is cleared when the DSP reads the receive data register or cleared by
hardware, software, SSI individual, or STOP reset. If RIE is set, a DSP receive data inter-
rupt request will be issued when RDF is set. The vector of the interrupt request will depend
on the state of the receiver overrun bit.
6.4.2.3.9
SSI Receive Shift Register
This 24-bit shift register receives the incoming data from the serial receive data pin. Data
is shifted in by the selected (internal/external) bit clock when the associated frame sync
I/O (or gated clock) is asserted. Data is assumed to be received MSB first if SHFD equals
zero and LSB first if SHFD equals one. Data is transferred to the SSI receive data register
after 8, 12, 16, or 24 bits have been shifted in, depending on the word-length control bits
in the CRA (see Figure 6-47).
6.4.2.3.10
SSI Receive Data Register (RX)
RX is a 24-bit read-only register that accepts data from the receive shift register as it be-
comes full. The data read will occupy the most significant portion of the receive data reg-
ister (see Figure 6-47). The unused bits (least significant portion) will read as zeros. The
DSP is interrupted whenever RX becomes full if the associated interrupt is enabled.
6.4.2.3.11
SSI Transmit Shift Register
This 24-bit shift register contains the data being transmitted. Data is shifted out to the se-
rial transmit data pin by the selected (internal/external) bit clock when the associated
frame sync I/O (or gated clock) is asserted. The number of bits shifted out before the shift
register is considered empty and may be written to again can be 8, 12, 16, or 24 bits (de-
termined by the word-length control bits in CRA). The data to be transmitted occupies the
most significant portion of the shift register. The unused portion of the register is ignored.
Data is shifted out of this register MSB first if SHFD equals zero and LSB first if SHFD
equals one (see Figure 6-48).
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Freescale Semiconductor, Inc.
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