HOST INTERFACE (HI)
5 - 60
PORT B
MOTOROLA
1. Set up the external DMA controller (1) source address, byte count, direction,
and other control registers. Enable the DMA controller channel.
2. Initialize the HI (2) by writing the ICR to select the word size (HM0 and HM1),
to select the direction (TREQ=1, RREQ=0), and to initialize the channel setting
INIT=1 (see Figure 5-38).
3. Initialize the DSP’s destination pointer (3) used in the DMA exception handler
(an address register, for example) and set HRIE to enable the HRDF interrupt
to the DSP CPU. This procedure can be done with a separate host command
exception routine in the DSP. HREQ will be asserted (4) immediately by the HI
to begin the DMA transfer.
4. Perform other tasks (5) while the DMA controller transfers data (6) until inter-
rupted by the DMA controller DMA transfer complete interrupt (7). The DSP
interrupt control register (ICR), the interrupt status register (ISR), and RXH,
RXM, and RXL registers may be accessed at any time by the host processor
but the TXH, TXM and TXL registers may not be accessed until the DMA
mode is disabled.
5. Terminate the DMA controller channel (8) to disable DMA transfers.
6. Terminate the DSP HI DMA mode (9) in the ICR by clearing the HM1 and HM0
bits and clearing TREQ.
The HREQ will be active immediately after initialization is completed (depending on hard-
ware) because the data direction is host to DSP and TXH, TXM, and TXL registers are
empty. When the host writes data to TXH, TXM, and TXL, this data will be immediately
transferred to HRX. If the DSP is due to work in interrupt mode, HRIE must be enabled.
5.3.6.3.3
DSP to Host Internal Processing
The following procedure outlines the steps that the HI hardware takes to transfer DMA
data from DSP memory to the host data bus.
1. On the DSP side of the HI, a host transmit exception will be generated when
HTDE=1 and HTIE=1. The exception routine must write HTX, thereby setting
HTDE=0.
2. If RXDF=0 and HTDE=0, the contents of HTX will be automatically transferred
to RXH:RXM:RXL, thereby setting RXDF=1 and HTDE=1. Since HTDE=1
again on the initial transfer, a second host transmit exception will be generated
immediately, and HTX will be written, which will clear HTDE again.
3. When RXDF is set to one, the HI’s internal DMA address counter is loaded
(from HM1 and HM0) and HREQ is asserted.
4. The DMA controller enables the data from the appropriate byte register onto
H0-H7 by asserting HACK. When HACK is asserted, HREQ is deasserted by
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Freescale Semiconductor, Inc.
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