TIMER/EVENT COUNTER MODES OF OPERATION
MOTOROLA
DSP56002 TIMER AND EVENT COUNTER
7 - 7
The TS bit is cleared when the TCSR is read. The bit is also cleared when the timer interrupt
is serviced (timer interrupt acknowledge). TS is cleared by hardware and software resets.
7.4.7
Direction (DIR) Bit 8
The DIR bit determines the behavior of the TIO pin when TIO acts as general purpose I/O.
When DIR=0, the TIO pin acts as an input. When DIR=1, the TIO pin acts as an output.
DIR is cleared by hardware and software resets.
Note:
The TIO pin can act as a general purpose I/O pin only when TC2-TC0 are all zero
and
the GPIO bit is set. If one of TC2, TC1 or TC0 is not 0, the GPIO function is
disabled and the DIR bit has no effect.
7.4.8
Data Input (DI) Bit 9
When the TIO pin acts as a general purpose I/O input pin (TC2-TC0 are all zero and
DIR=0), the contents of the DI bit will reflect the value the TIO pin. However, if the INV bit
is set, the data in DI will be inverted. When GPIO mode is disabled or it is enabled in out-
put mode (DIR=1), the DI bit reflects the value of the TIO pin, again depending on the
status of the INV bit. DI is set by hardware and software resets.
7.4.9
Data Output (DO) Bit 10
When the TIO pin acts as a general purpose I/O output pin (TC2-TC0 are all zero and
DIR=1), writing to the DO bit writes the data to the TIO pin. However, if the INV bit is set,
the data written to the TIO pin will be inverted. When GPIO mode is disabled, writing to
the DO bit will have no effect. DO is cleared by hardware and software resets.
7.4.10
TCSR Reserved bits (Bits 11-23)
These reserved bits are read as zero and should be written with zero for future compatibility.
7.5
TIMER/EVENT COUNTER MODES OF OPERATION
This section gives the details of each of the timer modes of operation. Table 7-1 on page
7-6 summarizes the items which determine the timer mode, including the configuration of
the timer control bits, the function of the TIO pin, and the clock source.
7.5.1
Timer Mode 0 (Standard Timer Mode, Internal Clock, No Timer Output)
Timer Mode 0 is defined by TCSR bits TC2-TC0 equal to 000.
With the timer enabled (TE=1), the counter is loaded with the value contained by the TCR. The
counter is decremented by a clock derived from the internal DSP clock, divided by two (CLK/2).
During the clock cycle following the point where the counter reaches 0, the TS bit is set and the
timer generates an interrupt. The counter is reloaded with the value contained by the TCR, and
the entire process is repeated until the timer is disabled (TE=0). Figure 7-3 illustrates Mode 0
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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