HOST INTERFACE (HI)
MOTOROLA
PORT B
5 - 51
the bits are set at 101 respectively, the DSP will load from the HI. Data is written by the
host processor in a pattern of four bytes, with the high byte being a dummy and the low
byte being the low byte of the DSP word (see Figure 5-29 and Figure 5-30). Figure 5-30
shows how an 8-,16-, 24-, or 32-bit word in the host processor maps into the HI registers.
The HI register at address $4 is not used and will read as zero. It is not necessary to use
address $4, but since many host processors are 16- or 32-bit processors, address $4 will
often be used as part of the 16- or 32-bit word. The low order byte (at $7) should always
be written last since writing to it causes the HI to initiate the transfer of the word to the
HRX. Data is then transferred from the HRX to the DSP program memory. If the host
processor needs to terminate the bootstrap loading before 512 words have been down
loaded, it can set the HF0 bit in the ICR. The DSP will then terminate the down load and
start executing at location P:$0000. Since the DSP56002 is typically faster than the host
processor, hand shaking during the data transfer is normally not required.
The actual code used in the bootstrap program is given in APPENDIX A. The portion of
the code that loads from the HI is shown in Figure 5-31. The BSET instruction configures
HOST
DATA
HIGH
MIDDLE
LOW
READ - 00000000
WRITE - XXXXXXXX
HOST
TRANSMIT/RECEIVE
BYTE REGISTERS
7
0
HOST BYTE
ADDRESS
4
5
6
7
0 0 0 0 0 0 0 0
TXH/RXH
HIGH BYTE
TXM/RXM
MIDDLE BYTE
TXL/RXL
LOW BYTE
31
24 23
16 15
8 7
0
8-BIT TRANSFER
16-BIT TRANSFER
24-BIT TRANSFER
32-BIT TRANSFER, LS 24 BITS ARE SIGNIFICANT
ACCESS TO
LOW BYTE
INITIATES
TRANSFER
NOTE: Access low byte last
Figure 5-30 Transmit/Receive Byte Registers
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
.
..
