SERIAL COMMUNICATION INTERFACE (SCI)
6 - 18
PORT C
MOTOROLA
6.3.2.1.2
SCR SCI Shift Direction (SSFTD) Bit 3
The SCI data shift registers can be programmed to shift data in/out either LSB first if
SSFTD equals zero, or MSB first if SSFTD equals one. The parity and data type bits do
not change position and remain adjacent to the stop bit. SSFTD is cleared by hardware
and software reset.
6.3.2.1.3
SCR Send Break (SBK) Bit 4
A break is an all-zero word frame – a start bit zero, a character of all zeros (including any
parity), and a stop bit zero: i.e., 10 or 11 zeros depending on the WDS mode selected. If
SBK is set and then cleared, the transmitter completes transmission of any data, sends
10 or 11 zeros, and reverts to idle or sending data. If SBK remains set, the transmitter will
continually send whole frames of zeros (10 or 11 bits with no stop bit). At the completion
of the break code, the transmitter sends at least one high bit before transmitting any data
to guarantee recognition of a valid start bit. Break can be used to signal an unusual con-
dition, message, etc. by forcing a frame error, which is caused by a missing stop bit.
Hardware and software reset clear SBK.
6.3.2.1.4
SCR Wakeup Mode Select (WAKE) Bit 5
When WAKE equals zero, an idle line wakeup is selected. In the idle line wakeup mode,
the SCI receiver is re-enabled by an idle string of at least 10 or 11 (depending on WDS
mode) consecutive ones. The transmitter’s software must provide this idle string between
consecutive messages. The idle string cannot occur within a valid message because each
word frame contains a start bit that is a zero.
When WAKE equals one, an address bit wakeup is selected. In the address bit wakeup
mode, the SCI receiver is re-enabled when the last (eighth or ninth) data bit received in a
character (frame) is one. The ninth data bit is the address bit (R8) in the 11-bit multidrop
mode; the eighth data bit is the address bit in the 10-bit asynchronous and 11-bit asyn-
chronous with parity modes. Thus, the received character is an address that has to be pro-
cessed by all sleeping processors – i.e., each processor has to compare the received
character with its own address and decide whether to receive or ignore all following char-
acters. WAKE is cleared by hardware and software reset.
6.3.2.1.5
SCR Receiver Wakeup Enable (RWU) Bit 6
When RWU equals one and the SCI is in an asynchronous mode, the wakeup function is
enabled – i.e., the SCI is put to sleep waiting for a reason (defined by the WAKE bit) to
wakeup. In the sleeping state, all receive flags, except IDLE, and interrupts are disabled.
When the receiver wakes up, this bit is cleared by the wakeup hardware. The programmer
may also clear the RWU bit to wake up the receiver.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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