BUS ARBITRATION AND SHARED MEMORY
MOTOROLA
PORT A
4 - 23
The DSP56K processor series has a group of instructions designed to prevent this prob-
lem. They perform an indivisible read-modify-write operation and do not release the bus
between the read and write (specifically, A0–A15, DS, PS, and X/Y do not change state).
Using a read-modify-write operation allows these instructions to test the sema-
phore and then to set, clear, or change the semaphore without the possibility of
another processor testing the semaphore before it is changed. The instructions are
bit test and change (BCHG), bit test and clear (BCLR), and bit test and set (BSET).
(They are discussed in detail in the DSP56000 Family Manual.) The proper way to set
the semaphore to gain exclusive access to a memory block is to use BSET to test the
semaphore and to set it to one. After the bit is set, the result of the test operation will
reveal if the semaphore was clear before it was set by BSET and if the memory block is
available. If the bit was already set and the block is in use by another processor, the DSP
must wait to access the memory block.
ADDRESS
DATA AND
CONTROL
BUSES
ADDRESS
DATA AND
CONTROL
BUSES
SEMAPHORE 3
SEMAPHORE 2
SEMAPHORE 1
SEMAPHORE 0
1
1
0
0
BANK 3
BANK 2
BANK 1
BANK 0
DSP56002
PROCESSOR
OR DMA
DSP56002
LOCAL
MEMORY
PROCESSOR
LOCAL
MEMORY
ARBITRATION
LOGIC
BUS
BUFFER
BUS
BUFFER
Figure 4-17 Signaling Using Semaphores
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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