SERIAL COMMUNICATION INTERFACE (SCI)
6 - 22
PORT C
MOTOROLA
6.3.2.1.14
SCR SCI Clock Polarity (SCKP) Bit 15
The clock polarity, sourced or received on the clock pin (SCLK), can be inverted using this
bit, eliminating the need for an external inverter. When bit 15 equals zero, the clock polar-
ity is positive; when bit 15 equals one, the clock polarity is negative. In the synchronous
mode, positive polarity means that the clock is normally positive and transitions negative
during data valid; whereas, negative polarity means that the clock is normally negative
and transitions positive during valid data. In the asynchronous mode, positive polarity
means that the rising edge of the clock occurs in the center of the period that data is valid;
negative polarity means that the falling edge of the clock occurs during the center of the
period that data is valid. SCKP is cleared on hardware and software reset.
6.3.2.2
SCI Status Register (SSR)
The SSR is an 8-bit read-only register used by the DSP CPU to determine the status of
the SCI. When the SSR is read onto the internal data bus, the register contents occupy
the low-order byte of the data bus and all high-order portions are zero filled. The status
bits are described in the following paragraphs.
6.3.2.2.1
SSR Transmitter Empty (TRNE) Bit 0
The TRNE flag is set when both the transmit shift register and data register are empty to
indicate that there is no data in the transmitter. When TRNE is set, data written to one of
the three STX locations or to the STXA will be transferred to the transmit shift register and
be the first data transmitted. TRNE is cleared when TDRE is cleared by writing data into
the transmit data register (STX) or the transmit data address register (STXA), or when an
idle, preamble, or break is transmitted. The purpose of this bit is to indicate that the trans-
mitter is empty; therefore, the data written to STX or STXA will be transmitted next – i.e.,
there is not a word in the transmit shift register presently being transmitted. This proce-
dure is useful when initiating the transfer of a message (i.e., a string of characters). TRNE
is set by the hardware, software, SCI individual, and stop reset.
6.3.2.2.2
SSR Transmit Data Register Empty (TDRE) Bit 1
The TDRE bit is set when the SCI transmit data register is empty. When TDRE is set, new
data may be written to one of the SCI transmit data registers (STX) or transmit data ad-
dress register (STXA). TDRE is cleared when the SCI transmit data register is written.
TDRE is set by the hardware, software, SCI individual, and stop reset.
In the SCI synchronous mode, when using the internal SCI clock, there is a delay of up to
5.5 serial clock cycles between the time that STX is written until TDRE is set, indicating
the data has been transferred from the STX to the transmit shift register. There is a two
to four serial clock cycle delay between writing STX and loading the transmit shift register;
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Freescale Semiconductor, Inc.
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