SYNCHRONOUS SERIAL INTERFACE (SSI)
6 - 78
PORT C
MOTOROLA
This interface is descriptively named “synchronous” because all serial transfers are syn-
chronized to a clock. Additional synchronization signals are used to delineate the word
frames. The normal mode of operation is used to transfer data at a periodic rate, but only
one word per period. The network mode is similar in that it is also intended for periodic
transfers; however, it will support up to 32 words (time slots) per period. This mode can
be used to build time division multiplexed (TDM) networks. In contrast, the on-demand
mode is intended for nonperiodic transfers of data. This mode can be used to transfer data
serially at high speed when the data becomes available. This mode offers a subset of the
SPI protocol.
6.4.1
SSI Data and Control Pins
The SSI has three dedicated I/O pins (see Figure 6-1), which are used for transmit data
(STD), receive data (SRD), and serial clock (SCK), where SCK may be used by both the
transmitter and the receiver for synchronous data transfers or by the transmitter only for
asynchronous data transfers. Three other pins may also be used, depending on the mode
selected; they are serial control pins SC0, SC1, and SC2. They may be programmed as
SSI control pins in the Port C control register. Table 6-5 shows the definition of SC0, SC1,
SC2, and SCK in the various configurations. The following paragraphs describe the uses
of these pins for each of the SSI operating modes. Figure 6-42 and Figure 6-43 show the
internal clock path connections in block diagram form. The receiver and transmitter clocks
can be internal or external depending on the SYN, SCD0, and SCKD bits in CRB.
6.4.1.1
Serial Transmit Data Pin (STD)
STD is used for transmitting data from the serial transmit shift register. STD is an output
when data is being transmitted. Data changes on the positive edge of the bit clock. STD
goes to high impedance on the negative edge of the bit clock of the last data bit of the
word (i.e., during the second half of the last data bit period) with external gated clock, re-
gardless of the mode. With an internally generated bit clock, the STD pin becomes high
impedance after the last data bit has been transmitted for a full clock period, assuming
another data word does not follow immediately. If a data word follows immediately, there
will not be a high-impedance interval.
Codecs label the MSB as bit 0; whereas, the DSP labels the LSB as bit 0. Therefore, when
using a standard codec, the DSP MSB (or codec bit 0) is shifted out first when SHFD=0, and
the DSP LSB (or codec bit 7) is shifted out first when SHFD=1. STD may be programmed
as a general-purpose pin called PC8 when the SSI STD function is not being used.
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Freescale Semiconductor, Inc.
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