BUS ARBITRATION AND SHARED MEMORY
4 - 16
PORT A
MOTOROLA
state logic to establish the start of an external access. BS is deasserted in T3 of each
external bus cycle, signaling that the current bus cycle will complete. Since the WT signal
is internally synchronized, it can be asserted asynchronously with respect to the system
clock. The WT signal should only be asserted while BS is asserted. Asserting WT while
BS is deasserted will give indeterminate results. However, for the number of inserted wait
states to be deterministic, WT timing must satisfy setup and hold timing with respect to the
negative-going edge of EXTAL. The setup and hold times are provided in the
DSP56002
Advance Information Data Sheet (DSP56002/D)
. The timing of WR is controlled by the
BCR and is independent of WT. The minimum number of wait states that can be inserted
using the WT pin is two. The BCR is still operative when using BS and WT and defines
the minimum number of wait states that are inserted. Table 4-2 summarizes the effect of
the BCR and WT pin on the number of wait states generated.
4.7
BUS ARBITRATION AND SHARED MEMORY
The DSP56002 has five pins that control port A. They are bus needed (BN), bus request
(BR), bus grant (BG), bus strobe (BS) and bus wait (WT) and they are described in SEC-
TION 2 DSP56002 PIN DESCRIPTIONS.
The bus control signals provide the means to connect additional bus masters (which may be
additional DSPs, microprocessors, direct memory access (DMA) controllers, etc.) to the port
A bus. They work together to arbitrate and determine what device gets access to the bus.
If an external device has requested the external bus by asserting the BR input, and the
DSP has granted the bus by asserting BG, the DSP will continue to process as long as it
requires no external bus accesses itself. If the DSP does require an external access but
is not the bus master, it will stop processing and remain in wait states until it regains bus
ownership. The BN pin will have been asserted, and an external device may use BN to
help “arbitrate”, or decide when to return bus ownership to the chip.
Four examples of bus arbitration will be described later in this section: 1) bus arbitration
using only BR and BG with internal control, 2) bus arbitration using BN, BR, and BG with
external control, 3) bus arbitration using BR, BG and WT, BS with no overhead, and 4)
signaling using semaphores.
The BR input allows an external device to request and be given control of the external bus
while the DSP continues internal operations using internal memory spaces. This allows a
bus controller to arbitrate a multiple bus-master system. (A bus master can issue
addresses on the bus; a bus slave can respond to addresses on the bus. A single device
can be both a master and a slave, but can only be one or the other at any given time.)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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