SYNCHRONOUS SERIAL INTERFACE (SSI)
MOTOROLA
PORT C
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frame is completed. If the frame sync goes high before the frame is completed (or before
the last bit of the frame is received in the case of a bit frame sync), the current frame sync
will not be recognized, and the receiver will be internally disabled until the next frame
sync. Frames do not have to be adjacent – i.e., a new frame sync does not have to imme-
diately follow the previous frame. Gaps of arbitrary periods can occur between frames.
The transmitter will be three-stated during these gaps.
6.4.7.1.5
Shift Direction Selection
Some data formats, such as those used by codecs, specify MSB first other data formats,
such as the AES-EBU digital audio, specify LSB first. To interface with devices from both
systems, the shift registers in the SSI are bidirectional. The MSB/LSB selection is made
by programming SHFD in the CRB.
Figure 6-71 illustrates the operation of the SHFD bit in the CRB. If SHFD equals zero (see
Figure 6-71(a)), data is shifted into the receive shift register MSB first and shifted out of
the transmit shift register MSB first. If SHFD equals one (see Figure 6-71(b)), data is shift-
ed into the receive shift register LSB first and shifted out of the transmit shift register LSB
first.
6.4.7.2
Normal Mode Examples
The normal SSI operating mode characteristically has one time slot per serial frame, and
data is transferred every frame sync. When the SSI is not in the normal mode, it is in the
network mode. The MSB is transmitted first (SHFD=0), with overrun and underrun errors
detected by the SSI hardware. Transmit flags are set when data is transferred from the
transmit data register to the transmit shift register. The receive flags are set when data is
transferred from the receive shift register to the receive data register.
Figure 6-72 shows an example of using the SSI to connect an MC15500 codec with a
DSP56002. No glue logic is needed. The serial clock, which is generated internally by the
DSP, provides the transmit and receive clocks (synchronous operation) for the codec.
SC2 provides all the necessary handshaking. Data transfer begins when the frame sync
is asserted. Transmit data is clocked out and receive data is clocked in with the serial
clock while the frame sync is asserted (word-length frame sync). At the end of the data
transfer, DSP internal interrupts programmed to transfer data to/from will occur, and the
SSISR will be updated.
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Freescale Semiconductor, Inc.
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