SERIAL COMMUNICATION INTERFACE (SCI)
MOTOROLA
PORT C
6 - 27
buffering. Double buffering provides flexibility and increased throughput since the pro-
grammer can save the previous word while the current word is being received.
The SRX can be read at three locations: X:$FFF4, X:$FFF5, and X:$FFF6 (see Figure
6-13). When location X:$FFF4 is read, the contents of the SRX are placed in the lower
byte of the data bus and the remaining bits on the data bus are written as zeros. Similarly,
when X:$FFF5 is read, the contents of SRX are placed in the middle byte of the bus, and
when X:$FFF6 is read, the contents of SRX are placed in the high byte with the remaining
bits zeroed. Mapping SRX as described allows three bytes to be efficiently packed into
TCM
RCM
TX Clock
RX Clock
SCLK Pin
Mode
0
0
Internal
Internal
Output
Synchronous/Asynchronous
0
1
Internal
External
Input
Asynchronous Only
1
0
External
Internal
Input
Asynchronous Only
1
1
External
External
Input
Synchronous/Asynchronous
f
osc
DIVIDE
BY 2
12-BIT COUNTER
PRESCALER:
DIVIDE BY
1 or 8
DIVIDE
BY 2
CD11 - CD0
SCP
INTERNAL CLOCK
DIVIDE
BY 16
TIMER
INTERRUPT
(STMINT)
SCI CORE LOGIC
USES DIVIDE BY 16 FOR
ASYNCHRONOUS
USES DIVIDE BY 2 FOR
SYNCHRONOUS
COD
SCKP
IF ASYNCHRONOUS
DIVIDE BY 1 OR 16
IF SYNCHRONOUS
DIVIDE BY 2
SCKP = 0
+
SCKP = 1
-
TO SCLK
fo
BPS = 64 x (7(SCP) + 1) x CD + 1)
where:
SCP = 0 or 1
CD = 0 to $FFF
Figure 6-12 SCI Baud Rate Generator
STIR
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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