SERIAL COMMUNICATION INTERFACE (SCI)
MOTOROLA
PORT C
6 - 41
window is from the time TDRE goes high halfway into transmission of bit 1 until the middle
of bit 6 (see Figure 6-19(a)).
As a peripheral (synchronous slave) shown in Figure 6-18, the DSP accepts an input clock
from the SCLK pin. If SCKP equals zero, data is clocked in on the rising edge of SCLK,
and data is clocked out on the falling edge of SCLK. If SCKP equals one, data is clocked
in on the falling edge of SCLK, and data is clocked out on the rising edge of SCLK. The
slave mode is selected by choosing external transmit and receive clocks (TCM and
RCM=1). Since there is no frame signal, if a clock is missed due to noise or any other rea-
son, the receiver will lose synchronization with the data without any error signal being gen-
erated. Detecting an error of this type can be done with an error detecting protocol or with
external circuitry such as a watchdog timer. The simplest way to recover synchronization
is to reset the SCI.
The timing diagram in Figure 6-18 shows transmit data in the normal driven mode. Bit B7
is essentially one-half SCI clock long (T
SCI
/2 + 1.5 T
EXTAL
) The last data bit is truncated
so that the pin is guaranteed to go to its reset state before the start of the next data word,
thereby delimiting data words. The 1.5 crystal clock cycles provide sufficient hold time to
satisfy most external logic requirements. The example diagram requires that the WOMS
bit be set in the SCR to wired-OR RXD and TXD, which causes TXD to be three-stated
when not transmitting. Collisions (two devices transmitting simultaneously) must be avoid-
ed with this circuit by using a protocol such as alternating transmit and receive periods. In
the example, the 8051 is the master device because it controls the clock. There is a win-
dow during which STX must be written with the next byte to be transmitted to prevent the
current word from being retransmitted. This window is from the time TDRE goes high,
which is halfway into the transmission of bit 1, until the middle of bit 6 (see Figure 6-19(b)).
Of course, this assumes the clock remains continuous – i.e., there is a second word. If the
clock stops, the SCI stops.
The DSP is initially configured according to the protocol to either receive data or transmit data.
If the protocol determines that the next data transfer will be a DSP transmit, the DSP will con-
figure the SCI for transmit and load STX (or STXA). When the master starts SCLK, data will
be ready and waiting. If the protocol determines that the next data transfer will be a DSP re-
ceive, the DSP will configure the SCI for receive and will either poll the SCI or enable inter-
rupts. This methodology allows multiple slave processors to use the same data line. Selection
of individual slave processors can be under protocol control or by multiplexing SCLK.
Note: TCM=0, RCM=1 and TCM=1,RCM=0 are not allowed in the synchronous mode.
The results are undefined.
The assembly program shown in Figure 6-20 uses the SCI synchronous mode to transmit
only the low byte of the Y data ROM contents. The program sets the reset vector to run
the program after a hardware reset, puts the MOVEP instruction at the SCI transmit inter-
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Freescale Semiconductor, Inc.
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