SERIAL COMMUNICATION INTERFACE (SCI)
6 - 30
PORT C
MOTOROLA
The transmit shift register is not directly addressable, and a dedicated flag for this register
does not exist. Because of this fact and the two to four cycle delay, two bytes cannot be
written consecutively to STX or STXA without polling. The second byte will overwrite the
first byte. The TDRE flag should always be polled prior to writing STX or STXA to prevent
overruns unless transmit interrupts have been enabled. Either STX or STXA is usually
written as part of the interrupt service routine. Of course, the interrupt will only be gener-
ated if TDRE equals one. The transmit shift register is indirectly visible via the TRNE bit
in the SSR.
In the synchronous modes, data is synchronized with the transmit clock, which may have
either an internal or external source as defined by the TCM bit in the SCCR. The length
and format of the serial word is defined by the WDS0, WDS1, and WDS2 control bits in
the SCR. In the asynchronous modes, the start bit, the eight data bits (with the LSB first
if SSFTD=0 and the MSB first if SSFTD=1), the address/data indicator bit or parity bit, and
the stop bit are transmitted in that order (see Figure 6-10).
The data to be transmitted can be written to any one of the three STX addresses. If SCKP
equals one and SSHTD equals one, the SCI synchronous mode is equivalent to the SSI
operation in the 8-bit data on-demand mode.
6.3.2.5
Preamble, Break, and Data Transmission Priority
It is possible that two or three transmission commands are set simultaneously:
1. A preamble (TE was toggled)
2. A break (SBK was set or was toggled)
3. There is data for transmission (TDRE=0)
After the current character transmission, if two or more of these commands are set, the
transmitter will execute them in the following priority:
1. Preamble
2. Break
3. Data
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Freescale Semiconductor, Inc.
For More Information On This Product,
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