HOST INTERFACE (HI)
5 - 42
PORT B
MOTOROLA
1.
When the TXDE bit in the ISR is set, it indicates that the HI is ready to receive
a data byte from the host processor because the transmit byte registers (TXH,
TXM, TXL) are empty.
2.
The host processor can poll as shown in this step.
3.
Alternatively, the host processor can use interrupts to determine the status of
this bit. Setting the TREQ bit in the ICR causes the HREQ pin to interrupt the
host processor when TXDE is set.
4.
Once the TXDE bit is set, the host can write data to the HI. It does this by writ-
ing three bytes to TXH, TXM, and TXL, respectively, or two bytes to TXM and
TXL, respectively, or one byte to TXL.
5.
Writing data to TXL clears TXDE in the ISR.
6.
From the DSP’s viewpoint, the HRDF bit (when set) in the HSR indicates that
data is waiting in the HI for the DSP.
INIT
HM1
HM0
HF1
HF0
TREQ RREQ
$0
*Reserved; write as zero.
7
6
5
4
3
2
1
0
INITIALIZE DSP
INITIALIZE HI**
BIT 7 = 1
OPTIONAL
INTERRUPT CONTROL REGISTER (ICR)
(READ/WRITE)
DMA OFF
BIT 5 = 0
BIT 6 = 0
STEP 2 OF HOST PORT CONFIGURATION
2. OPTION 3: SELECT INTERRUPT MODE FOR
ENABLE
RECEIVE DATA FULL INTERRUPT
BIT 0 = 1
BIT 1 = 0
ENABLE
TRANSMIT DATA EMPTY INTERRUPT
BIT 0 = 0
BIT 1 = 1
DSP TO HOST
OR
HOST TO DSP
OR
DSP TO HOST
AND
HOST TO DSP
IV7
IV6
IV5
IV4
IV3
IV2
IV1
IV0
$3
7
6
5
4
3
2
1
0
INTERRUPT VECTOR REGISTER (IVR)
(READ/WRITE)
2. OPTION 4: LOAD HOST INTERRUPT VECTOR IF USING THE INTERRUPT MODE AND THE HOST PROCESSOR REQUIRES AN
INTERRUPT VECTOR.
**See Figure 10 - 23.
ENABLE
RECEIVE DATA FULL INTERRUPT AND
TRANSMIT DATA EMPTY INTERRUPT
BIT 0 = 1
BIT 1 = 1
*
Figure 5-21 (c) HI Initialization–Host Side, Interrupt Mode
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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