GENERAL PURPOSE I/O CONFIGURATION
5 - 4
PORT B
MOTOROLA
5.2
GENERAL PURPOSE I/O CONFIGURATION
When it is configured as general-purpose I/O, Port B acts as three memory-mapped reg-
isters (see Figure 5-2) that control 15 I/O pins (see Figure 5-3). They are the Port B control
register (PBC), Port B data direction register (PBDDR), and Port B data register (PBD).
The software and hardware resets clear the PBC and PBDDR, which configures Port B
as general-purpose I/O, with all 15 pins as inputs. (External circuitry connected to these
pins may need pullups until the pins are configured for operation.)
To select between general purpose I/O and the HI, set PBC bits 0 and 1 as shown in Fig-
ure 5-2. Use the PBDDR to determine whether the corresponding bit in the PBD shall be
an input pin (bit is set to zero) or an output pin (bit is set to one).
If a pin is configured as a GPIO
input
(as shown in Figure 5-4) and the processor reads
the PBD, the processor sees the logic level on the pin. If the processor writes to the PBD,
the data is latched there, but does not appear on the pin because the buffer is in the high-
impedance state.
BC1
BC0
Function
0
0
Parallel I/O (Reset Condition)
0
1
Host Interface
1
0
Host Interface (with HACK pin as GPIO)
1
1
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BC
0
23
0
X:$FFE0
PORT B CONTROL
REGISTER (PBC)
BD
0
23
0
X:$FFE2
PORT B DATA
DIRECTION
REGISTER (PBDDR)
BDx
Data Direction
0
Input (Reset Condition)
1
Output
0
0
0
0
0
0
0
0
0
BD
1
BD
2
BD
3
BD
4
BD
5
BD
6
BD
7
BD
8
BD
9
BD
11
BD
10
BD
12
BD
13
BD
14
PB
0
23
0
X:$FFE4
PORT B DATA
REGISTER (PBD)
0
0
0
0
0
0
0
0
0
PB
1
PB
2
PB
3
PB
4
PB
5
PB
6
PB
7
PB
8
PB
9
PB
11
PB
10
PB
12
PB
13
PB
14
Figure 5-2 Parallel Port B Registers
BC
1
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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