242
CHAPTER 11 MULTIFUNCTIONAL TIMER
■
PPG Control Register, Lower Byte (PICSL01)
EG01 EG00
Edge selection bit (input capture 0)
0
0
Edge is not detected (stop)
0
1
Rising edge is detected.
1
0
Falling edge is detected.
1
1
Both edge are detected.
EG11 EG10
Edge selection bit (input capture 1)
0
0
Edge is not detected (stop)
0
1
Rising edge is detected.
1
0
Falling edge is detected.
1
1
Both edge are detected.
ICE0
Interrupt request enable bit (input capture 0)
0
Disable interrupt request
1
Enable interrupt request
ICE1
Interrupt request enable bit (input capture 1)
0
Disable interrupt request
1
Enable interrupt request
Interrupt request flag bit (input capture 0)
ICP0
Read
Write
0
Valid edge is not detected.
This bit is cleared.
1
Valid edge is detected.
No effect on this bit.
Interrupt request flag bit (input capture 1)
ICP1
Read
Write
0
Valid edge is not detected.
This bit is cleared.
1
Valid edge is detected.
No effect on this bit.
ICP1
ICP0
ICE1
ICE0
EG11
EG10
EG01
EG00
Output control register (Lo
w
er)
PICSL01
Address: 0000B5
H
R/W: Read/Write
Initial value: 00000000
B
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
: Initial value
Summary of Contents for FR60Lite
Page 3: ......
Page 5: ......
Page 115: ...100 CHAPTER 3 CPU AND CONTROL UNITS ...
Page 127: ...112 CHAPTER 4 I O PORTS ...
Page 143: ...128 CHAPTER 5 INTERRUPT CONTROLLER ...
Page 155: ...140 CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER ...
Page 197: ...182 CHAPTER 9 PPG Programmable Pulse Generator ...
Page 337: ...322 CHAPTER 13 UART ...
Page 417: ...402 CHAPTER 16 DMAC DMA Controller ...
Page 445: ...430 CHAPTER 17 FLASH MEMORY ...
Page 451: ...436 CHAPTER 18 SERIAL PROGRAMMING CONNECTION ...
Page 493: ...478 APPENDIX F Precautions on Handling ...
Page 494: ...479 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...
Page 507: ...492 INDEX ...
Page 509: ......