372
CHAPTER 16 DMAC (DMA Controller)
•
Writing "1" to this bit is ignored and DMA remains halted if operation has been disabled for all channels
by the DMAE bit (bit15 of the overall DMAC control register DMACR). Also, if operation is disabled
by the aforementioned bit while still enabled by this bit, this bit is cleared to "0" and transfer is aborted
(forcibly halted).
[bit30] PAUS (PAUSe): Pause indication
Pauses DMA transfer for the corresponding channel. No DMA transfer is performed from the time this bit
is set until it is cleared again. (The DSS bits go to "1xx
B
" when DMA is halted.)
If this bit is set before DMA is enabled, DMA remains paused.
New transfer requests are accepted while this bit is set but the transfers do not start until the bit is cleared.
(See "
■
Transfer Request Acceptance and Transfer".)
•
Initialized to "0" when resetting.
•
The read / write is possible.
[bit29] STRG (Software TRiGger): Transfer request
Generates a DMA transfer request for the corresponding channel. Writing "1" to this bit generates a transfer
request as soon as the register write completes and starts the transfer on the corresponding channel.
However, if the corresponding channel is not enabled, writing to this bit is ignored.
Note:
If a transfer request is set via this bit at the same time as start is enabled by the DMAE bit, the
transfer request is valid and transfer starts. If this bit is written to at the same time as writing "1" to
the PAUS bit, the transfer request is valid, but DMA transfer does not start until the PAUS bit is
cleared to "0".
•
Initialized to "0" when resetting.
•
Reading always returns "0".
•
Only writing "1" is meaningful. Writing "0" has no effect on the operation.
PAUS
Function
0
Corresponding channel DMA is enabled to operate (initial value).
1
Corresponding channel DMA is suspended.
STRG
Function
0
Not provided
1
DMA activating request
Summary of Contents for FR60Lite
Page 3: ......
Page 5: ......
Page 115: ...100 CHAPTER 3 CPU AND CONTROL UNITS ...
Page 127: ...112 CHAPTER 4 I O PORTS ...
Page 143: ...128 CHAPTER 5 INTERRUPT CONTROLLER ...
Page 155: ...140 CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER ...
Page 197: ...182 CHAPTER 9 PPG Programmable Pulse Generator ...
Page 337: ...322 CHAPTER 13 UART ...
Page 417: ...402 CHAPTER 16 DMAC DMA Controller ...
Page 445: ...430 CHAPTER 17 FLASH MEMORY ...
Page 451: ...436 CHAPTER 18 SERIAL PROGRAMMING CONNECTION ...
Page 493: ...478 APPENDIX F Precautions on Handling ...
Page 494: ...479 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...
Page 507: ...492 INDEX ...
Page 509: ......