463
APPENDIX E Instruction Lists
Appendix Table E-1 Addition and Subtraction
Mnemonic
Type
OP
CYCLE
NZVC
Operation
Remarks
ADD Rj, Ri
*ADD #s5, Ri
ADD #u4, Ri
ADD2 #u4, Ri
A
C’
C
C
A6
A4
A4
A5
1
1
1
1
CCCC
CCCC
CCCC
CCCC
Ri+Rj->Ri
Ri+s5->Ri
Ri+extu(i4)->Ri
Ri+extu(i4)->Ri
The assembler treats the
highest-order 1 bit as the
sign.
Zero extension
Minus extension
ADDN Rj, Ri
A
A7
1
CCCC
Ri+Rj+c->Ri
Addition with carry
ADDN Rj, Ri
*ADDN #s5, Ri
ADDN #u4, Ri
ADDN2 #u4, Ri
A
C’
C
C
A2
A0
A0
A1
1
1
1
1
----
----
----
----
Ri+Rj->Ri
Ri+s5->Ri
Ri+extu(i4)->Ri
Ri+extu(i4)->Ri
The assembler treats the
highest-order 1 bit as the
sign.
Zero extension
Minus extension
SUB Rj, Ri
A
AC
1
CCCC
Ri-Rj->Ri
SUBC Rj, Ri
A
AD
1
CCCC
Ri-Rj-c->Ri
Subtraction with carry
SUBN Rj, Ri
A
AE
1
----
Ri-Rj->Ri
Appendix Table E-2 Comparison Operation
Mnemonic
Type
OP
CYCLE
NZVC
Operation
Remarks
CMP Rj, Ri
*CMP #s5, Ri
CMP #u4, Ri
CMP2 #u4, Ri
A
C’
C
C
AA
A8
A8
A9
1
1
1
1
CCCC
CCCC
CCCC
CCCC
Ri-Rj
Ri-s5
Ri-extu(i4)
Ri-extu(i4)
The assembler treats the
highest-order 1 bit as the sign.
Zero extension
Minus extension
Summary of Contents for FR60Lite
Page 3: ......
Page 5: ......
Page 115: ...100 CHAPTER 3 CPU AND CONTROL UNITS ...
Page 127: ...112 CHAPTER 4 I O PORTS ...
Page 143: ...128 CHAPTER 5 INTERRUPT CONTROLLER ...
Page 155: ...140 CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER ...
Page 197: ...182 CHAPTER 9 PPG Programmable Pulse Generator ...
Page 337: ...322 CHAPTER 13 UART ...
Page 417: ...402 CHAPTER 16 DMAC DMA Controller ...
Page 445: ...430 CHAPTER 17 FLASH MEMORY ...
Page 451: ...436 CHAPTER 18 SERIAL PROGRAMMING CONNECTION ...
Page 493: ...478 APPENDIX F Precautions on Handling ...
Page 494: ...479 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...
Page 507: ...492 INDEX ...
Page 509: ......