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Silicon Laboratories EFM32JG1, Reference Manual

The Silicon Laboratories EFM32JG1 Reference Manual is available for free download on our website. This comprehensive manual covers all aspects of using this high-performance product, providing valuable insights and instructions. Visit 88.208.23.73:8080 to easily access and download this essential manual for optimizing your experience with the EFM32JG1.

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22.3.8.10  ADC as a Random Number Generator

The ADC can be used as a random number generator. This is done by:

1. Choose the REF in the ADCn_SINGLECTRL as CONF, setting the VREFSEL in the ADCn_SINGLECTRLX as VENTROPY and

VINATT in the same register to its maximum value of 15.

2. Set DIFF to 1 and RES to 0 in the ADCn_SINGLECTRL register.
3. Trigger a single channel conversion and then read ADCn_SINGLEDATA register when the conversion finishes.

The LSB[2:0] of each sample will be a random number. In this mode, the POSSEL or NEGSEL in ADCn_SINGLECTRL can be connec-
ted to VSS or any other noisy input.

22.3.9  Interrupts, PRS Output

The single and scan modes have separate SINGLE and SCAN interrupt flags indicating whether corresponding FIFO contains DVL # of
valid conversion data. Corresponding interrupt enable bit has to be set in ADCn_IEN in order to generate interrupts. For these inter-
rupts, there is no software clear mechanism by writing to ADCn_IFC. The user needs to read enough data from the interrupted FIFO to
ensure  it  contains  less  than  DVL  #  of  elements.  The  ADCn_SINGLEFIFOCOUNT/ADCn_SCANFIFOCOUNT  can  provide  number  of
valid  elements  remaining  in  corresponding  FIFO.  The  FIFO  can  also  be  cleared  by  ADCn_SINGLEFIFOCLEAR/ADCn_SCANFIFO-
CLEAR, but any existing data will be lost by this operation.

In addition to the SINGLE and SCAN interrupt flags, there is separate scan and single channel result overflow interrupt flag which sig-
nals that a result from a scan or single channel FIFO has been overwritten before being read. There is also separate scan and single
channel result underflow interrupt flag which signals that a FIFO read was issued when the FIFO was empty.

There  is  separate  scan  and  single  compare  interrupt  flag  which  signals  a  compare  match  with  latest  sample  if  the  CMPEN  in
ADCn_SINGLECTRL/ADCn_SCANCTRL is enabled.

ADC  has  two  separate  PRS  outputs,  one  for  single  channel  and  one  for  scan  sequence.  A  finished  conversion  results  in  a  one
ADC_CLK cycle pulse, which is output to the Peripheral Reflex System (PRS). Note that the PRS pulse for scan is generated once after
every channel conversion in the scan sequence.

22.3.10  DMA Request

The ADC has two DMA request lines, SINGLEREQ and SCANREQ, which are set when a single or scan FIFO receives DVL# of sam-
ples. The requests are cleared when the corresponding single or scan result register is read and corresponding FIFO count reaches
lower  than  DVL.  It  also  has  two  additional  DMA  Single  request  lines,  SINGLESREQ  and  SCANSREQ,  that  are  set  when  the  corre-
sponding FIFO is not empty.

22.3.11  Calibration

The ADC supports offset and gain calibration to correct errors due to process and temperature variations. This must be done individual-
ly for each reference used. For each reference, it needs to be repeated for single-ended, negative single-ended (see 

22.3.5 Input Se-

lection

 for details) and differential measurement. The ADC calibration (ADCn_CAL) register contains register fields for calibrating offset

and gain for both single and scan mode. The gain and offset calibration are done in single channel mode, but the resulting calibration
values can be used for both single and scan mode.

Gain and offset for various references and modes are calibrated during production and the calibration values for these can be found in
the Device Information page. During reset, the gain and offset calibration registers are loaded with the production calibration values for
the 1V25 reference. Others can be loaded as needed or the user can perform calibration on the fly using the particular reference and
mode to be used and write the result in the ADCn_CAL before starting the ADC conversion with them.

EFM32JG1 Reference Manual

ADC - Analog to Digital Converter

silabs.com

 | Smart. Connected. Energy-friendly.

Preliminary Rev. 0.6  |  737

Summary of Contents for EFM32JG1

Page 1: ...th and fitness Smart accessories Home automation and security Industrial and factory automation Peripheral Reflex System 32 bit bus Core Memory Lowest power mode with peripheral operational EM2 Deep Sleep EM1 Sleep EM4 Hibernate EM4 Shutoff EM0 Active EM3 Stop Serial Interfaces USART Low Energy UARTTM I2 C I O Ports Timers and Triggers CRYOTIMER Real Time Counter and Calendar Other CRYPTO CRC Anal...

Page 2: ...als in the EFM32 Jade Gecko devices are described in general terms Not all modules are present in all devices and the feature set for each device might vary Such differences including pinout are covered in the device data sheets EFM32JG1 Reference Manual About This Document silabs com Smart Connected Energy friendly Preliminary Rev 0 6 1 ...

Page 3: ...egister descriptions are explained in Table 1 1 Register Access Types on page 2 Table 1 1 Register Access Types Access Type Description R Read only Writes are ignored RW Readable and writable RW1 Readable and writable Only writes to 1 have effect R W1 Sometimes readable Only writes to 1 have effect Currently only used for IFC registers see 3 3 1 2 IFC Read clear Operation W1 Read value undefined O...

Page 4: ...ven with a module prefix followed by a short pin name CMU_CLKOUT1 Clock management unit clock output pin number 1 The location for the pin names given in the module documentation can be found in the device specific datasheet 1 3 Related Documentation Further documentation on the EFM32 Jade Gecko devices and the ARM Cortex M3 can be found at the Silicon Labs and ARM web pages www silabs com www arm...

Page 5: ...application as well as other systems requiring high performance and low energy consumption 2 1 Introduction The EFM32 MCUs are the world s most energy friendly microcontrollers With a unique combination of the powerful 32 bit ARM Cortex M3 innovative low energy techniques short wake up time from energy saving modes and a wide selection of peripherals the EFM32 Jade Gecko microcontroller is well su...

Page 6: ...ounter Low Energy Timer Pulse Counter Watchdog Timer External Interrupts General Purpose I O Pin Reset Pin Wakeup Flash Program Memory RAM Memory ARM CortexTM M3 processor Debug Interface DMA Controller Energy Management Brown Out Detector DC DC Converter Voltage Regulator Voltage Monitor Power On Reset Clock Management Low Frequency Crystal Oscillator High Frequency RC Oscillator Ultra Low Freque...

Page 7: ... Accelerated SHA 1 and SHA 2 Accelerated Elliptic Curve Cryptography ECC with binary or prime fields Flexible 256 bit ALU and sequencer General Purpose Cyclic Redundancy Check Programmable 16 bit polynomial fixed 32 bit polynomial Communication interfaces 2 Universal Synchronous Asynchronous Receiver Transmitter UART SPI SmartCard ISO 7816 IrDA I2S Triple buffered full half duplex operation Hardwa...

Page 8: ... as alternative clock source for Analog to Digital Converter or Debug Trace LFRCO 32768 Hz No Medium accuracy frequency reference typically used for medi um accuracy RTCC timing LFXO 32768 Hz Yes Crystal High accuracy frequency reference typically used for high ac curacy RTCC timing Tunable crystal loading capacitors are fully integrated ULFRCO 1000 Hz No Ultra low frequency oscillator typically u...

Page 9: ... the CCM mode can be implemented using the CTR and CBC MAC modes in combination Table 2 2 AES modes of operation with hardware support AES Mode Encryption Decryption Authentication Comment ECB Yes Electronic Code Book CTR Yes Counter mode CCM Yes Yes Counter with CBC MAC CCM Yes Yes CCM with encryption only and integrity only capabilities GCM Yes Yes Galois Counter Mode CBC Yes Cipher Block Chaini...

Page 10: ...Cortex M3 Typically used as an Operating System timer WDOG 1 Low frequency LFXO LFRCO or ULFRCO Watch dog timer Once enabled this module must be periodically accessed If not this is consid ered an error and the EFM32 Jade Gecko is reset in order to recover the system LETIMER 1 Low frequency LFXO LFRCO or ULFRCO Low energy general purpose timer Advanced interconnect features allows synchronization ...

Page 11: ...umption budget How Combined with the ultra low energy peripherals available in EFM32 Jade Gecko devices the Cortex M3 processor s Harvard architecture 3 stage pipe line single cycle instructions Thumb 2 instruction set support and fast interrupt handling make it per fect for 8 bit 16 bit and 32 bit applications 3 1 Introduction The ARM Cortex M3 32 bit RISC processor provides outstanding computati...

Page 12: ...t migration choice for 8 16 bit architecture based designs Simplified stack based programmer s model is compatible with traditional ARM architecture and retains the programming simplici ty of legacy 8 bit and 16 bit architectures Alligned or unaligned data storage and access Contiguous storage of data requiring different byte lengths Data access in a single core access cycle Integrated power modes...

Page 13: ...errupts There can be latencies in the system such that clearing an interrupt flag could take longer than leaving an Interrupt Service Routine ISR This can lead to the ISR being re entered as the interrupt flag has yet to clear immediately after leaving the ISR To avoid this when clearing an interrupt flag at the end of an ISR the user should execute ARM s Data Synchronization Barrier DSB instructi...

Page 14: ...EN 10 TIMER0 11 USART0_RX 12 USART0_TX 13 ACMP0 14 ADC0 15 IDAC0 16 I2C0 17 GPIO_ODD 18 TIMER1 19 USART1_RX 20 USART1_TX 21 LEUART0 22 PCNT0 23 CMU 24 MSC 25 CRYPTO 26 LETIMER0 29 RTCC 31 CRYOTIMER 33 FPUEH EFM32JG1 Reference Manual System Processor silabs com Smart Connected Energy friendly Preliminary Rev 0 6 13 ...

Page 15: ... interfaces to the AHB slaves Figure 4 1 EFM32 Jade Gecko Bus System on page 14 The bus matrix allows several AHB slaves to be accessed simultaneously An AMBA APB interface is used for the peripher als which are accessed through an AHB to APB bridge connected to the AHB bus matrix The 4 AHB bus masters are Cortex M3 ICode Used for instruction fetches from Code memory valid address range 0x00000000...

Page 16: ...stem Address Space with Core and Code Space Listing on page 15 Figure 4 2 System Address Space with Core and Code Space Listing Additionally the peripheral address map is detailed by Figure 4 3 System Address Space with Peripheral Listing on page 16 EFM32JG1 Reference Manual Memory and Bus System silabs com Smart Connected Energy friendly Preliminary Rev 0 6 15 ...

Page 17: ...tack other data in SRAM and peripherals using the System bus interface To be able to run code from SRAM efficiently the SRAM is also mapped in the code space at address 0x10000000 When running code from this space the Cortex M3 fetches instructions through the I D Code bus interface leaving the System bus interface for data access The SRAM mapped into the code space can however only be accessed by...

Page 18: ...ord back to the register or SRAM address Using bit banding this can be done in a single operation consuming only two bus cycles As read writeback bit masking and bit shift operations are not necessary in software code size is reduced and execution speed improved The bit band regions allow each bit in the SRAM and Peripheral areas of the memory map to be addressed To set or clear a bit in the embed...

Page 19: ...gister register register OR mask For bit clear operations bit locations that are 1 in the bit mask will be cleared in the destination register register register AND NOT mask Note It is possible to combine bit clear and bit set operations in order to arbitrarily modify multi bit register fields without affecting other fields in the same register In this case care should be taken to ensure that the ...

Page 20: ...0x4000A000 0x4000B000 GPIO 0x40006000 0x40006400 IDAC0 0x40002000 0x40002400 ADC0 0x40000400 0x40000800 ACMP1 0x40000000 0x40000400 ACMP0 Table 4 3 Low Energy Peripherals Address Range Module Name 0x40052000 0x40052400 WDOG0 0x4004E000 0x4004E400 PCNT0 0x4004A000 0x4004A400 LEUART0 0x40046000 0x40046400 LETIMER0 0x40042000 0x40042400 RTCC Table 4 4 Core Peripherals Address Range Module Name 0x400F...

Page 21: ...est case write accesses Nbus cycles Nslave cycles fHFBUSCLK fHFPERCLK 1 best case read accesses Nbus cycles Nslave cycles 1 fHFBUSCLK fHFPERCLK 1 worst case write accesses Nbus cycles Nslave cycles 1 fHFBUSCLK fHFPERCLK worst case read accesses where Nslave cycles is the number of cycles required to access the particular slave including any wait cycles introduced by the slave Figure 4 4 Bus Access...

Page 22: ...ow register accesses are performed as described in the following sections 4 3 1 Writing Every Low Energy Peripheral has one or more registers with data that needs to be synchronized into the Low Energy clock domain to maintain data consistency and predictable operation There are two different synchronization mechanisms on the EFM32JG1 immedi ate synchronization and delayed synchronization Immediat...

Page 23: ...uency Clock High Frequency Clock Domain Low Frequency Clock Domain Write request 0 Write request 1 Write request n Figure 4 9 Write operation to Low Energy Peripherals 4 3 1 2 Immediate Synchronization In contrast to the peripherals with delayed synchronization peripherals with immediate synchronization don t experience a delay from a value is written to it takes effect in the peripheral They are ...

Page 24: ... all Low Energy Peripheral with delayed synchronization there is a module_name _FREEZE register e g RTCC_FREEZE The register contains a bit named REGFREEZE If precise control of the synchronization process is required this bit may be utilized When REGFREEZE is set the synchronization process is halted allowing the software to write multiple Low Energy registers before starting the synchronization ...

Page 25: ...n of the entire memory in EM0 Active to EM3 Stop The SRAM memory may be split among two or more different AHB slaves e g RAM0 RAM1 in order to allow simultaneous ac cess to different sections of the memory from two different AHB masters For example the Cortex M3 can access RAM0 while the DMA controller accesses RAM1 in parallel See Figure 4 1 EFM32 Jade Gecko Bus System on page 14 for AHB slave co...

Page 26: ...er 2 0x06C ADC0CAL3 RO ADC0 calibration register 3 0x080 HFRCOCAL0 RO HFRCO Calibration Register 4 MHz 0x08C HFRCOCAL3 RO HFRCO Calibration Register 7 MHz 0x098 HFRCOCAL6 RO HFRCO Calibration Register 13 MHz 0x09C HFRCOCAL7 RO HFRCO Calibration Register 16 MHz 0x0A0 HFRCOCAL8 RO HFRCO Calibration Register 19 MHz 0x0A8 HFRCOCAL10 RO HFRCO Calibration Register 26 MHz 0x0AC HFRCOCAL11 RO HFRCO Calibr...

Page 27: ...CLPCMPHYSSEL0 RO DCDC LPCMPHYSSEL Trim Register 0 0x180 DCDCLPCMPHYSSEL1 RO DCDC LPCMPHYSSEL Trim Register 1 4 7 DI Page Entry Description 4 7 1 CAL CRC of DI page and calibration temperature Offset Bit Position 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access RO RO Name TEMP CRC Bit Name Access Description 31 24 Reserved Reserved for future use 23...

Page 28: ...1 10 9 8 7 6 5 4 3 2 1 0 Access RO Name OUI48H Bit Name Access Description 31 16 Reserved Reserved for future use 15 0 OUI48H RO Upper two Octets of EUI48 Organizationally Unique Identifier 4 7 4 CUSTOMINFO Custom information Offset Bit Position 0x030 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access RO Name PARTNO Bit Name Access Description 31 16 PARTNO...

Page 29: ...IZE 10 0xFF Ie the value 0xFF 512 bytes 23 16 PINCOUNT RO Device pin count as unsigned integer eg 48 15 8 PKGTYPE RO Package Identifier as character Value Mode Description 74 WLCSP WLCSP package 77 QFN QFN package 81 QFP QFP package 7 0 TEMPGRADE RO Temperature Grade of product as unsigned inte ger enumeration Value Mode Description 0 N40TO85 40 to 85degC 1 N40TO125 40 to 125degC 2 N40TO105 40 to ...

Page 30: ...5 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access RO Name UNIQUEH Bit Name Access Description 31 0 UNIQUEH RO High 32 bits of device unique number 4 7 8 MSIZE Flash and SRAM Memory size in kB Offset Bit Position 0x048 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access RO RO Name SRAM FLASH Bit Name Access Description 31 16 SRAM RO Ram size kbyte count as unsigne...

Page 31: ... Device Family 25 EFR32FG1P EFR32 Flex Gecko Gen1 Device Family 26 EFR32FG1B EFR32 Flex Gecko Gen1 Device Family 27 EFR32FG1V EFR32 Flex Gecko Gen1 Device Family 71 EFM32G EFM32 Gecko Device Family 71 G EFM32 Gecko Device Family 72 EFM32GG EFM32 Giant Gecko Device Family 72 GG EFM32 Giant Gecko Device Family 73 TG EFM32 Tiny Gecko Device Family 73 EFM32TG EFM32 Tiny Gecko Device Family 74 EFM32LG ...

Page 32: ... 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access RO Name DEVINFOREV Bit Name Access Description 31 8 Reserved Reserved for future use 7 0 DEVINFOREV RO DEVINFO layout revision as unsigned integer initial ly 1 4 7 11 EMUTEMP EMU Temperature Calibration Information Offset Bit Position 0x054 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access...

Page 33: ...ed Reserved for future use 30 24 GAIN2V5 RO Gain for 2 5V reference 23 20 NEGSEOFFSET2V5 RO Negative single ended offset for 2 5V reference 19 16 OFFSET2V5 RO Offset for 2 5V reference 15 Reserved Reserved for future use 14 8 GAIN1V25 RO Gain for 1 25V reference 7 4 NEGSEOFFSET1V25 RO Negative single ended offset for 1 25V reference 3 0 OFFSET1V25 RO Offset for 1 25V reference EFM32JG1 Reference M...

Page 34: ...ture use 30 24 GAIN5VDIFF RO Gain for for 5V differential reference 23 20 NEGSEOFFSET5VDIFF RO Negative single ended offset with for 5V differential reference 19 16 OFFSET5VDIFF RO Offset for 5V differential reference 15 Reserved Reserved for future use 14 8 GAINVDD RO Gain for VDD reference 7 4 NEGSEOFFSETVDD RO Negative single ended offset for VDD reference 3 0 OFFSETVDD RO Offset for VDD refere...

Page 35: ...served for future use 7 4 NEGSEOFFSET2XVDD RO Negative single ended offset for 2XVDD reference 3 0 OFFSET2XVDD RO Offset for 2XVDD reference 4 7 15 ADC0CAL3 ADC0 calibration register 3 Offset Bit Position 0x06C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access RO Name TEMPREAD1V25 Bit Name Access Description 31 16 Reserved Reserved for future use 15 4 TEM...

Page 36: ...Coefficient Trim on Comparator Reference 27 FINETUNINGEN RO HFRCO enable reference for fine tuning 26 25 CLKDIV RO HFRCO Clock Output Divide 24 LDOHP RO HFRCO LDO High Power Mode 23 21 CMPBIAS RO HFRCO Comparator Bias Current 20 16 FREQRANGE RO HFRCO Frequency Range 15 14 Reserved Reserved for future use 13 8 FINETUNING RO HFRCO Fine Tuning Value 7 Reserved Reserved for future use 6 0 TUNING RO HF...

Page 37: ...Coefficient Trim on Comparator Reference 27 FINETUNINGEN RO HFRCO enable reference for fine tuning 26 25 CLKDIV RO HFRCO Clock Output Divide 24 LDOHP RO HFRCO LDO High Power Mode 23 21 CMPBIAS RO HFRCO Comparator Bias Current 20 16 FREQRANGE RO HFRCO Frequency Range 15 14 Reserved Reserved for future use 13 8 FINETUNING RO HFRCO Fine Tuning Value 7 Reserved Reserved for future use 6 0 TUNING RO HF...

Page 38: ... Coefficient Trim on Comparator Reference 27 FINETUNINGEN RO HFRCO enable reference for fine tuning 26 25 CLKDIV RO HFRCO Clock Output Divide 24 LDOHP RO HFRCO LDO High Power Mode 23 21 CMPBIAS RO HFRCO Comparator Bias Current 20 16 FREQRANGE RO HFRCO Frequency Range 15 14 Reserved Reserved for future use 13 8 FINETUNING RO HFRCO Fine Tuning Value 7 Reserved Reserved for future use 6 0 TUNING RO H...

Page 39: ... Coefficient Trim on Comparator Reference 27 FINETUNINGEN RO HFRCO enable reference for fine tuning 26 25 CLKDIV RO HFRCO Clock Output Divide 24 LDOHP RO HFRCO LDO High Power Mode 23 21 CMPBIAS RO HFRCO Comparator Bias Current 20 16 FREQRANGE RO HFRCO Frequency Range 15 14 Reserved Reserved for future use 13 8 FINETUNING RO HFRCO Fine Tuning Value 7 Reserved Reserved for future use 6 0 TUNING RO H...

Page 40: ... Coefficient Trim on Comparator Reference 27 FINETUNINGEN RO HFRCO enable reference for fine tuning 26 25 CLKDIV RO HFRCO Clock Output Divide 24 LDOHP RO HFRCO LDO High Power Mode 23 21 CMPBIAS RO HFRCO Comparator Bias Current 20 16 FREQRANGE RO HFRCO Frequency Range 15 14 Reserved Reserved for future use 13 8 FINETUNING RO HFRCO Fine Tuning Value 7 Reserved Reserved for future use 6 0 TUNING RO H...

Page 41: ... Coefficient Trim on Comparator Reference 27 FINETUNINGEN RO HFRCO enable reference for fine tuning 26 25 CLKDIV RO HFRCO Clock Output Divide 24 LDOHP RO HFRCO LDO High Power Mode 23 21 CMPBIAS RO HFRCO Comparator Bias Current 20 16 FREQRANGE RO HFRCO Frequency Range 15 14 Reserved Reserved for future use 13 8 FINETUNING RO HFRCO Fine Tuning Value 7 Reserved Reserved for future use 6 0 TUNING RO H...

Page 42: ... Coefficient Trim on Comparator Reference 27 FINETUNINGEN RO HFRCO enable reference for fine tuning 26 25 CLKDIV RO HFRCO Clock Output Divide 24 LDOHP RO HFRCO LDO High Power Mode 23 21 CMPBIAS RO HFRCO Comparator Bias Current 20 16 FREQRANGE RO HFRCO Frequency Range 15 14 Reserved Reserved for future use 13 8 FINETUNING RO HFRCO Fine Tuning Value 7 Reserved Reserved for future use 6 0 TUNING RO H...

Page 43: ... Coefficient Trim on Comparator Reference 27 FINETUNINGEN RO HFRCO enable reference for fine tuning 26 25 CLKDIV RO HFRCO Clock Output Divide 24 LDOHP RO HFRCO LDO High Power Mode 23 21 CMPBIAS RO HFRCO Comparator Bias Current 20 16 FREQRANGE RO HFRCO Frequency Range 15 14 Reserved Reserved for future use 13 8 FINETUNING RO HFRCO Fine Tuning Value 7 Reserved Reserved for future use 6 0 TUNING RO H...

Page 44: ...cient Trim on Compa rator Reference 27 FINETUNINGEN RO AUXHFRCO enable reference for fine tuning 26 25 CLKDIV RO AUXHFRCO Clock Output Divide 24 LDOHP RO AUXHFRCO LDO High Power Mode 23 21 CMPBIAS RO AUXHFRCO Comparator Bias Current 20 16 FREQRANGE RO AUXHFRCO Frequency Range 15 14 Reserved Reserved for future use 13 8 FINETUNING RO AUXHFRCO Fine Tuning Value 7 Reserved Reserved for future use 6 0...

Page 45: ...cient Trim on Compa rator Reference 27 FINETUNINGEN RO AUXHFRCO enable reference for fine tuning 26 25 CLKDIV RO AUXHFRCO Clock Output Divide 24 LDOHP RO AUXHFRCO LDO High Power Mode 23 21 CMPBIAS RO AUXHFRCO Comparator Bias Current 20 16 FREQRANGE RO AUXHFRCO Frequency Range 15 14 Reserved Reserved for future use 13 8 FINETUNING RO AUXHFRCO Fine Tuning Value 7 Reserved Reserved for future use 6 0...

Page 46: ...cient Trim on Compa rator Reference 27 FINETUNINGEN RO AUXHFRCO enable reference for fine tuning 26 25 CLKDIV RO AUXHFRCO Clock Output Divide 24 LDOHP RO AUXHFRCO LDO High Power Mode 23 21 CMPBIAS RO AUXHFRCO Comparator Bias Current 20 16 FREQRANGE RO AUXHFRCO Frequency Range 15 14 Reserved Reserved for future use 13 8 FINETUNING RO AUXHFRCO Fine Tuning Value 7 Reserved Reserved for future use 6 0...

Page 47: ...cient Trim on Compa rator Reference 27 FINETUNINGEN RO AUXHFRCO enable reference for fine tuning 26 25 CLKDIV RO AUXHFRCO Clock Output Divide 24 LDOHP RO AUXHFRCO LDO High Power Mode 23 21 CMPBIAS RO AUXHFRCO Comparator Bias Current 20 16 FREQRANGE RO AUXHFRCO Frequency Range 15 14 Reserved Reserved for future use 13 8 FINETUNING RO AUXHFRCO Fine Tuning Value 7 Reserved Reserved for future use 6 0...

Page 48: ...cient Trim on Compa rator Reference 27 FINETUNINGEN RO AUXHFRCO enable reference for fine tuning 26 25 CLKDIV RO AUXHFRCO Clock Output Divide 24 LDOHP RO AUXHFRCO LDO High Power Mode 23 21 CMPBIAS RO AUXHFRCO Comparator Bias Current 20 16 FREQRANGE RO AUXHFRCO Frequency Range 15 14 Reserved Reserved for future use 13 8 FINETUNING RO AUXHFRCO Fine Tuning Value 7 Reserved Reserved for future use 6 0...

Page 49: ...icient Trim on Compa rator Reference 27 FINETUNINGEN RO AUXHFRCO enable reference for fine tuning 26 25 CLKDIV RO AUXHFRCO Clock Output Divide 24 LDOHP RO AUXHFRCO LDO High Power Mode 23 21 CMPBIAS RO AUXHFRCO Comparator Bias Current 20 16 FREQRANGE RO AUXHFRCO Frequency Range 15 14 Reserved Reserved for future use 13 8 FINETUNING RO AUXHFRCO Fine Tuning Value 7 Reserved Reserved for future use 6 ...

Page 50: ...icient Trim on Compa rator Reference 27 FINETUNINGEN RO AUXHFRCO enable reference for fine tuning 26 25 CLKDIV RO AUXHFRCO Clock Output Divide 24 LDOHP RO AUXHFRCO LDO High Power Mode 23 21 CMPBIAS RO AUXHFRCO Comparator Bias Current 20 16 FREQRANGE RO AUXHFRCO Frequency Range 15 14 Reserved Reserved for future use 13 8 FINETUNING RO AUXHFRCO Fine Tuning Value 7 Reserved Reserved for future use 6 ...

Page 51: ...icient Trim on Compa rator Reference 27 FINETUNINGEN RO AUXHFRCO enable reference for fine tuning 26 25 CLKDIV RO AUXHFRCO Clock Output Divide 24 LDOHP RO AUXHFRCO LDO High Power Mode 23 21 CMPBIAS RO AUXHFRCO Comparator Bias Current 20 16 FREQRANGE RO AUXHFRCO Frequency Range 15 14 Reserved Reserved for future use 13 8 FINETUNING RO AUXHFRCO Fine Tuning Value 7 Reserved Reserved for future use 6 ...

Page 52: ...RSE RO ALTAVDD 2 98 V Coarse Threshold Adjust 27 24 ALTAVDD2V98THRESFINE RO ALTAVDD 2 98 V Fine Threshold Adjust 23 20 ALTAVDD1V86THRESCOARSE RO ALTAVDD 1 86 V Coarse Threshold Adjust 19 16 ALTAVDD1V86THRESFINE RO ALTAVDD 1 86 V Fine Threshold Adjust 15 12 AVDD2V98THRESCOARSE RO AVDD 2 98 V Coarse Threshold Adjust 11 8 AVDD2V98THRESFINE RO AVDD 2 98 V Fine Threshold Adjust 7 4 AVDD1V86THRESCOARSE ...

Page 53: ...SCOARSE RO IO0 2 98 V Coarse Threshold Adjust 27 24 IO02V98THRESFINE RO IO0 2 98 V Fine Threshold Adjust 23 20 IO01V86THRESCOARSE RO IO0 1 86 V Coarse Threshold Adjust 19 16 IO01V86THRESFINE RO IO0 1 86 V Fine Threshold Adjust 15 12 DVDD2V98THRESCOARSE RO DVDD 2 98 V Coarse Threshold Adjust 11 8 DVDD2V98THRESFINE RO DVDD 2 98 V Fine Threshold Adjust 7 4 DVDD1V86THRESCOARSE RO DVDD 1 86 V Coarse Th...

Page 54: ...ARSE RO FVDD 2 98 V Coarse Threshold Adjust 27 24 FVDD2V98THRESFINE RO FVDD 2 98 V Fine Threshold Adjust 23 20 FVDD1V86THRESCOARSE RO FVDD 1 86 V Coarse Threshold Adjust 19 16 FVDD1V86THRESFINE RO FVDD 1 86 V Fine Threshold Adjust 15 12 PAVDD2V98THRESCOARSE RO PAVDD 2 98 V Coarse Threshold Adjust 11 8 PAVDD2V98THRESFINE RO PAVDD 2 98 V Fine Threshold Adjust 7 4 PAVDD1V86THRESCOARSE RO PAVDD 1 86 V...

Page 55: ...Access Description 31 24 SOURCERANGE3TUNING RO Calibrated middle step 16 of current source mode range 3 23 16 SOURCERANGE2TUNING RO Calibrated middle step 16 of current source mode range 2 15 8 SOURCERANGE1TUNING RO Calibrated middle step 16 of current source mode range 1 7 0 SOURCERANGE0TUNING RO Calibrated middle step 16 of current source mode range 0 EFM32JG1 Reference Manual Memory and Bus Sys...

Page 56: ...nk mode range 1 7 0 SINKRANGE0TUNING RO Calibrated middle step 16 of current sink mode range 0 4 7 37 DCDCLNVCTRL0 DCDC Low noise VREF Trim Register 0 Offset Bit Position 0x168 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access RO RO RO RO Name 3V0LNATT1 1V8LNATT1 1V8LNATT0 1V2LNATT0 Bit Name Access Description 31 24 3V0LNATT1 RO DCDC LNVREF Trim for 3 0V ...

Page 57: ...AS0 Bit Name Access Description 31 24 1V8LPATT0LPCMPBIAS1 RO DCDC LPVREF Trim for 1 8V output LPATT 0 LPCMPBIAS 1 23 16 1V2LPATT0LPCMPBIAS1 RO DCDC LPVREF Trim for 1 2V output LPATT 0 LPCMPBIAS 1 15 8 1V8LPATT0LPCMPBIAS0 RO DCDC LPVREF Trim for 1 8V output LPATT 0 LPCMPBIAS 0 7 0 1V2LPATT0LPCMPBIAS0 RO DCDC LPVREF Trim for 1 2V output LPATT 0 LPCMPBIAS 0 EFM32JG1 Reference Manual Memory and Bus Sy...

Page 58: ...AS2 Bit Name Access Description 31 24 1V8LPATT0LPCMPBIAS3 RO DCDC LPVREF Trim for 1 8V output LPATT 0 LPCMPBIAS 3 23 16 1V2LPATT0LPCMPBIAS3 RO DCDC LPVREF Trim for 1 2V output LPATT 0 LPCMPBIAS 3 15 8 1V8LPATT0LPCMPBIAS2 RO DCDC LPVREF Trim for 1 8V output LPATT 0 LPCMPBIAS 2 7 0 1V2LPATT0LPCMPBIAS2 RO DCDC LPVREF Trim for 1 2V output LPATT 0 LPCMPBIAS 2 EFM32JG1 Reference Manual Memory and Bus Sy...

Page 59: ...AS0 Bit Name Access Description 31 24 3V0LPATT1LPCMPBIAS1 RO DCDC LPVREF Trim for 3 0V output LPATT 1 LPCMPBIAS 1 23 16 1V8LPATT1LPCMPBIAS1 RO DCDC LPVREF Trim for 1 8V output LPATT 1 LPCMPBIAS 1 15 8 3V0LPATT1LPCMPBIAS0 RO DCDC LPVREF Trim for 3 0V output LPATT 1 LPCMPBIAS 0 7 0 1V8LPATT1LPCMPBIAS0 RO DCDC LPVREF Trim for 1 8V output LPATT 1 LPCMPBIAS 0 EFM32JG1 Reference Manual Memory and Bus Sy...

Page 60: ...3V0LPATT1LPCMPBIAS2 RO DCDC LPVREF Trim for 3 0V output LPATT 1 LPCMPBIAS 3 7 0 1V8LPATT1LPCMPBIAS2 RO DCDC LPVREF Trim for 1 8V output LPATT 1 LPCMPBIAS 2 4 7 42 DCDCLPCMPHYSSEL0 DCDC LPCMPHYSSEL Trim Register 0 Offset Bit Position 0x17C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access RO RO Name LPCMPHYSSELLPATT1 LPCMPHYSSELLPATT0 Bit Name Access Descr...

Page 61: ...CMPHYSSELLPCMPBIAS1 LPCMPHYSSELLPCMPBIAS0 Bit Name Access Description 31 24 LPCMPHYSSELLPCMPBIAS3 RO DCDC LPCMPHYSSEL Trim LPCMPBIAS 3 23 16 LPCMPHYSSELLPCMPBIAS2 RO DCDC LPCMPHYSSEL Trim LPCMPBIAS 2 15 8 LPCMPHYSSELLPCMPBIAS1 RO DCDC LPCMPHYSSEL Trim LPCMPBIAS 1 7 0 LPCMPHYSSELLPCMPBIAS0 RO DCDC LPCMPHYSSEL Trim LPCMPBIAS 0 EFM32JG1 Reference Manual Memory and Bus System silabs com Smart Connecte...

Page 62: ...int Test Action Group JTAG interface For more technical information about the debug interface the reader is referred to ARM Cortex M3 Technical Reference Manual ARM CoreSight Components Technical Reference Manual ARM Debug Interface v5 Architecture Specification IEEE Standard for Test Access Port and Boundary Scan Architecture IEEE 1149 1 2013 5 2 Features Debug Access Port Serial Wire JTAG DAPSWJ...

Page 63: ...commands The command key must be writ ten with the correct key in order for the commands to execute 5 3 3 2 Device Erase The device can be erased by writing AAP_CMDKEY followed by writing the DEVICEERASE register bit Upon writing the command bit the ERASEBUSY bit is asserted The ERASEBUSY bit will be de asserted once the erase is complete The SYSRESETREQ bit must then be set to resume a normal deb...

Page 64: ...page is not erased The debugger may read the status of the device erase from the AAP_STATUS register When the ERASEBUSY bit is set low after DEVICEERASE of the AAP_CMD register is set the debugger may set the SYSRESETREQ bit in the AAP_CMD register After reset the debugger may resume a normal debug session through the AHB AP 5 3 5 AAP Lock Take extreme caution when using this feature Once the AAP ...

Page 65: ...RCSTATUS R CRC Status Register 0x018 AAP_CRCADDR RW CRC Address Register 0x01C AAP_CRCRESULT R CRC Result Register 0x0FC AAP_IDR R AAP Identification Register 5 5 Register Description 5 5 1 AAP_CMD Command Register Offset Bit Position 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 Access W1 W1 Name SYSRESETREQ DEVICEERASE Bit Name Reset Access...

Page 66: ...STATUS Status Register Offset Bit Position 0x008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 Access R R Name LOCKED ERASEBUSY Bit Name Reset Access Description 31 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 1 LOCKED 0 R AAP Locked Set when the AAP is locked e g the AAP Lock Wo...

Page 67: ...m bus is stalled Only the Cortex registers are accessible 5 5 5 AAP_CRCCMD CRC Command Register Offset Bit Position 0x010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 Access W1 Name CRCREQ Bit Name Reset Access Description 31 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 0 CRCREQ 0...

Page 68: ... Calculation is busy Set when the CRC calculation is executing Will transition from 1 to 0 on valid data 5 5 7 AAP_CRCADDR CRC Address Register Offset Bit Position 0x018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access RW Name CRCADDR Bit Name Reset Access Description 31 0 CRCADDR 0x00000000 RW Starting Page Address for CRC Execution Set...

Page 69: ...on using the CRCADDRESS 5 5 9 AAP_IDR AAP Identification Register Offset Bit Position 0x0FC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x26E60011 Access R Name ID Bit Name Reset Access Description 31 0 ID 0x26E60011 R AAP Identification Register Access port identification register in compliance with the ARM ADI v5 specification JEDEC Manufacturer ID...

Page 70: ...mp tion while eliminating the need for external program ming voltage to erase the memory An easy to use write and erase interface is supported by an internal fixed frequency oscillator and autonomous flash tim ing and control reduces software complexity while not using other timer resources Application code may dynamically scale between high energy optimization and high code execution performance ...

Page 71: ...e DMA write support in EM0 Active and EM1 Sleep Core clock independent Flash timing Internal oscillator and internal timers for precise and autonomous Flash timing General purpose timers are not occupied during Flash erase and write operations Configurable interrupt erase abort Improved interrupt predictability Memory and bus fault control Security features Lockable debug access Page lock bits SW ...

Page 72: ...erved 0x00040000 Reserved for flash ex pansion 24 MB Information 0 0x0FE00000 Software debug Yes User Data UD 2 KB 0x0FE00800 Reserved 1 0x0FE04000 Write Software debug Erase Debug only Yes Lock Bits LB 2 KB 0x0FE04800 Reserved 2 0x0FE081B0 Yes Device Information DI 1 KB 0x0FE08400 Reserved 2 0x0FE0C000 1 KB 0x0FE0C400 Reserved 3 0x0FE10000 Yes Bootloader BL 10 KB 7 0x0FE12000 Reserved 0x0FE12800 ...

Page 73: ... described in more detail in 5 3 3 Authentication Access Point Note that the AAP is only accessible from the debug interface and can not be accessed from the Cortex M3 core Word 125 is the mass erase lock word MLW Bit 0 locks the entire flash The mass erase lock bits will not have any effect on device erases initiated from the Authenitcation Access Port AAP registers The AAP is described in more d...

Page 74: ...is ready The system will wake up before this but the Cortex will stall on the first access to the flash until it is ready Execute code from RAM or cache to get a quicker startup To get the fastest possible startup when wakeup i e a startup that depends on the current operating conditions set STDLY0 to 0x28 and set ASTWAIT in MSC_STARTUP When configured this way the system will poll the flash to de...

Page 75: ...the Cortex M3 core prefetches both the next sequential instruction and the instruction at the branch target ad dress when a conditional branch instruction reaches the pipeline decode stage This prefetch scheme improves performance while one extra instruction is fetched from memory at each conditional branch regardless of whether the branch is taken or not To optimize for low energy the MSC can be ...

Page 76: ...ily To measure the hit rate of a code section the built in performance counters can be used Before the section start the performance counters by writing 1 to STARTPC in MSC_CMD This starts the performance counters counting from 0 At the end of the section stop the performance counters by writing 1 to STOPPC in MSC_CMD The number of cache hits and cache misses for that section can then be read from...

Page 77: ...ite the first word to the MSC_WDATA register and then set the WRITETRIG bit of the MSC_WRITECMD register DMA triggers when the WDATAREADY bit of the MSC_STATUS register is set It is possible to write words twice between each erase by keeping at 1 the bits that are not to be changed Let us take as an example writing two 16 bit values 0xAAAA and 0x5555 To safely write them in the same flash word thi...

Page 78: ...er 0x030 MSC_IF R Interrupt Flag Register 0x034 MSC_IFS W1 Interrupt Flag Set Register 0x038 MSC_IFC R W1 Interrupt Flag Clear Register 0x03C MSC_IEN RW Interrupt Enable Register 0x040 MSC_LOCK RWH Configuration Lock Register 0x044 MSC_CACHECMD W1 Flash Cache Command Register 0x048 MSC_CACHEHITS R Cache Hits Performance Counter 0x04C MSC_CACHEMISSES R Cache Misses Performance Counter 0x054 MSC_MAS...

Page 79: ...t when reading 1 IFC register reads the same value as IF and the corresponding inter rupt flags are cleared 2 PWRUPONDEMAND 0 RW Power Up On Demand During Wake Up When set during wake up pending AHB transfer will cause MSC to issue power up request to CMU If not set will always issue power up request if PWRUPONCMD is not set either 1 CLKDISFAULTEN 0 RW Clock disabled Bus Fault Response Enable When...

Page 80: ...24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0x1 0 1 0 0 0 Access RW RWH RW RW RW RW RW Name SCBTP MODE USEHPROT PREFETCH ICCDIS AIDIS IFCDIS EFM32JG1 Reference Manual MSC Memory System Controller silabs com Smart Connected Energy friendly Preliminary Rev 0 6 79 ...

Page 81: ...the frequency transition has been completed If the HFRCO is used as clock source wait until the oscillator is stable on the new frequency to avoid unpredictable behavior See Flash Wait States table for the corresponding threshold for different wait states Value Mode Description 0 WS0 Zero wait states inserted in fetch or read transfers 1 WS1 One wait state inserted for each fetch or read transfer ...

Page 82: ... always write bits to 0 More information in 1 2 Conven tions 1 IRQERASEABORT 0 RW Abort Page Erase on Interrupt When this bit is set to 1 any Cortex M4 interrupt aborts any current page erase operation Executing that interrupt vector from Flash will halt the CPU 0 WREN 0 RW Enable Write Erase Controller When this bit is set the MSC write and erase functionality is enabled EFM32JG1 Reference Manual...

Page 83: ...f the first word written to MSC_WDATA then add 4 to ADDR and write the next word if available within a 30us timeout When ADDR is incremented past the page boundary ADDR is set to the base of the page If WDOUBLE is set two words are required every time and ADDR is incremented by 8 3 WRITEONCE 0 W1 Word Write Once Trigger Write the word in MSC_WDATA to ADDR Flash access is returned to the AHB interf...

Page 84: ...aded into the internal MSC_ADDR register when the LADDRIM field in MSC_CMD is set 6 5 6 MSC_WDATA Write Data Register Offset Bit Position 0x018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access RW Name WDATA Bit Name Reset Access Description 31 0 WDATA 0x00000000 RW Write Data The data to be written to the address in MSC_ADDR This registe...

Page 85: ...his bit is set MSC_WDATA was not written within the timeout The flash write operation timed out and access to the flash is returned to the AHB interface This bit is cleared when the ERASEPAGE WRITETRIG or WRITEONCE commands in MSC_WRITECMD are triggered 3 WDATAREADY 1 R WDATA Write Ready When this bit is set the content of MSC_WDATA is read by MSC Flash Write Controller and the register may be upd...

Page 86: ...Parity Error Flag If one iCache RAM parity Error detected 4 PWRUPF 0 R Flash Power Up Sequence Complete Flag Set after MSC_CMD PWRUP received flash powered up complete and ready for read write 3 CMOF 0 R Cache Misses Overflow Interrupt Flag Set when MSC_CACHEMISSES overflows 2 CHOF 0 R Cache Hits Overflow Interrupt Flag Set when MSC_CACHEHITS overflows 1 WRITE 0 R Write Done Interrupt Read Flag Se...

Page 87: ...5 ICACHERR 0 W1 Set ICACHERR Interrupt Flag Write 1 to set the ICACHERR interrupt flag 4 PWRUPF 0 W1 Set PWRUPF Interrupt Flag Write 1 to set the PWRUPF interrupt flag 3 CMOF 0 W1 Set CMOF Interrupt Flag Write 1 to set the CMOF interrupt flag 2 CHOF 0 W1 Set CHOF Interrupt Flag Write 1 to set the CHOF interrupt flag 1 WRITE 0 W1 Set WRITE Interrupt Flag Write 1 to set the WRITE interrupt flag 0 ER...

Page 88: ...is feature must be enabled globally in MSC 3 CMOF 0 R W1 Clear CMOF Interrupt Flag Write 1 to clear the CMOF interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 2 CHOF 0 R W1 Clear CHOF Interrupt Flag Write 1 to clear the CHOF interrupt flag Reading returns the value of the IF and clears the corresponding inte...

Page 89: ...in 1 2 Conven tions 5 ICACHERR 0 RW ICACHERR Interrupt Enable Enable disable the ICACHERR interrupt 4 PWRUPF 0 RW PWRUPF Interrupt Enable Enable disable the PWRUPF interrupt 3 CMOF 0 RW CMOF Interrupt Enable Enable disable the CMOF interrupt 2 CHOF 0 RW CHOF Interrupt Enable Enable disable the CHOF interrupt 1 WRITE 0 RW WRITE Interrupt Enable Enable disable the WRITE interrupt 0 ERASE 0 RW ERASE ...

Page 90: ...00 RWH Configuration Lock Write any other value than the unlock code to lock access to MSC_CTRL MSC_READCTRL MSC_WRITECMD MSC_STARTUP and MSC_AAPUNLOCKCMD Write the unlock code to enable access When reading the register bit 0 is set when the lock is enabled Mode Value Description Read Operation UNLOCKED 0 MSC registers are unlocked LOCKED 1 MSC registers are locked Write Operation LOCK 0 Lock MSC ...

Page 91: ...erformance counters always start counting from 0 0 INVCACHE 0 W1 Invalidate Instruction Cache Use this register to invalidate the instruction cache 6 5 14 MSC_CACHEHITS Cache Hits Performance Counter Offset Bit Position 0x048 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000 Access R Name CACHEHITS Bit Name Reset Access Description 31 20 Reserved T...

Page 92: ... 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0001 Access RWH Name LOCKKEY Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 15 0 LOCKKEY 0x0001 RWH Mass Erase Lock Write any other value than the unlock code to lock access the the ERASEMAINn commands Write the unloc...

Page 93: ...s given by STWS during startup always 25 STWSEN 1 RW Startup Waitstates Enable Use the number of waitstates given by STWS during startup During the optional STDLY1 timeout 24 ASTWAIT 1 RW Active Startup Wait Active wait for flash startup startup after SDLY0 23 22 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 21 12 STDLY1 0x001 RW S...

Page 94: ...ccess Description 31 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 0 PWRUP 0 W1 Flash Power Up Command Write to this bit to power up the Flash IRQ PWRUPF will be fired when power up sequence completed EFM32JG1 Reference Manual MSC Memory System Controller silabs com Smart Connected Energy friendly Preliminary Rev 0 6 93 ...

Page 95: ...y configura ble prioritized DMA channels A linked list of flexible descriptors makes it possible to tailor the controller to the specific needs of an application 7 1 Introduction The Linked Direct Memory Access LDMA controller performs memory transfer operations independently of the CPU This has the benefit of reducing the energy consumption and the workload of the CPU and enables the system to st...

Page 96: ...cular and ping pong buffers Scatter Gather Looping Pause and restart triggered by other channels Sophisticated flow control which can function without CPU interaction Channel arbitration includes Fixed priority Simple round robin Round robin with programmable multiple interleaved entries for higher priority requesters Programmable data size and source and destination address strides Programmable i...

Page 97: ... Controller consists of three main parts A DMA core that executes transers and communicates status to the core A channel select block that routes peripheral DMA requests and acknowledge signals to the DMA A set of internal channel configuration registers for tracking the progres of each DMA channel The DMA has acces to all system memory through the AHB bus and the AHB APB bridge It can load channe...

Page 98: ...letion of a descriptor if the DONEIFSEN bit is set An AHB error will always generate an interrupt 7 3 1 Channel Descriptor Each DMA channel has descriptor registers A transfer can be initialized by software writing to the registers or by the DMA itself copying a descriptor from RAM to memory When using a linked list of descriptors the first descriptor should be initialized by the CPU The DMA itsel...

Page 99: ... loaded descriptor Note that the linked descriptor must be word aligned in memory The two least significant bits of the LDMA_CHx_LINK register are used by the LINK and LINKMODE bits The two least significant bits of the link address are always zero 7 3 1 7 Addressing Modes The DMA descriptors support absolute addressing or relative addressing When using relative addressing the offset is relative t...

Page 100: ...te swapped B3 B2 B1 B0 B3b7 B3b0 B2b7 B2b0 B1b7 B1b0 B0b7 B0b0 B3 B2 B1 B0 B3b7 B3b0 B2b7 B2b0 B1b7 B1b0 B0b7 B0b0 BYTESWAP 1 SIZE WORD B1 B0 B3b7 B3b0 B2b7 B2b0 B1b7 B1b0 B0b7 B0b0 B1 B0 B3b7 B3b0 B2b7 B2b0 B1b7 B1b0 B0b7 B0b0 BYTESWAP 1 SIZE HALF Figure 7 2 Word and Half Word Endian Byte Swap Examples EFM32JG1 Reference Manual LDMA Linked DMA Controller silabs com Smart Connected Energy friendly...

Page 101: ...B1 yB0 zB3 zB2 zB1 zB0 wB3 wB2 wB1 wB0 lB3 lB2 lB1 lB0 mB3 mB2 mB1 mB0 nB3 nB2 nB1 nB0 oB3 oB2 oB1 oB0 pB3 pB2 pB1 pB0 qB3 qB2 qB1 qB0 rB3 rB2 rB1 rB0 sB3 sB2 sB1 sB0 tB3 tB2 tB1 tB0 uB3 uB2 uB1 uB0 vB3 vB2 vB1 vB0 kB3 kB2 kB1 kB0 lB3 lB2 lB1 lB0 mB3 mB2 mB1 mB0 kB3 kB2 kB1 kB0 lB3 lB2 lB1 lB0 mB3 mB2 mB1 mB0 nB3 nB2 nB1 nB0 Next read data oB3 opB2 oB1 oB0 Next write data nB3 nB2 nB1 nB0 Figure 7 ...

Page 102: ...yB0 zB3 zB2 zB1 zB0 wB3 wB2 wB1 wB0 lB3 lB2 lB1 lB0 mB3 mB2 mB1 mB0 nB3 nB2 nB1 nB0 oB3 oB2 oB1 oB0 pB3 pB2 pB1 pB0 qB3 qB2 qB1 qB0 rB3 rB2 rB1 rB0 sB3 sB2 sB1 sB0 tB3 tB2 tB1 tB0 uB3 uB2 uB1 uB0 vB3 vB2 vB1 vB0 lB1 lB0 kB1 kB0 nB1 nB0 mB1 mB0 pB1 pB0 oB1 oB0 rB1 rB0 qB1 qB0 kB1 kB0 lB1 lB0 mB1 mB0 nB1 nB0 0x200 0x400 source destination Memory DMA Controller FIFO kB3 kB2 kB1 kB0 First read transmi...

Page 103: ...repeat a single descriptor the LINK address of the descriptor should point to itself After LOOPCNT reaches zero if the LINK bit in the descriptor LINK word is clear the transfer stops If the LINK bit is set the LDMA will load the next sequential descriptor located immediately following the looping descriptor The behavior of the LINK bit is different for a looping descriptor This is necessary becau...

Page 104: ...l with an active request is granted the transfer This mode guarantees smallest latency for the highest priority requesters It is best suited for systems where peak bandwidth is well below LDMA controller s maximum ability to serve The drawback of this mode is the possibility of starvation for lowest priority requesters In the round robin priority mode each active requesting channel is serviced in ...

Page 105: ... CHNL2_CFG ARBSLOTS ONE If all channels are constantly requesting transfers then the arbitration order is CHNL0 CHNL1 CHNL0 CHNL2 CHNL0 CHNL1 CHNL0 CHNL2 CHNL0 etc Note there are no channels assigned to arbitration slot four or eight in this exampl so thoes slots are skipped and the final sequence is ARBSLOT2 ARBSLOT1 ARBSLOT2 ARBSLOT1 etc Channel 1 and Channel 2 are selected in round robin order ...

Page 106: ... x 3 3 x 4 4 x 6 5 x 8 6 x 12 7 x 16 8 x 24 9 x 32 10 x 64 11 x 128 12 x 256 13 x 512 14 x 1024 15 x lock Note Software must take care not to assign a low priority channel with a large BLOCKSIZE because this prevents the controller from servic ing high priority requests until it re arbitrates The number of DMA transfers that need to be done is specified by the user in XFERCNT When XFERCNT BLOCKSIZ...

Page 107: ...ure This descriptor defines a typical data transfer which may be a Normal Link or Loop transfer Only this structure type can be written directly into LDMA s registers by the CPU All descriptors may be linked to Please refer to the register descriptions for additional information For specifying XFER structure type set STRUCTTYPE to 0 Please see the peripheral register descriptions for information o...

Page 108: ...CSET DST MATCHEN MATCHVAL LINK LINKADDR LINK LINKMODE Bit Name Description 1 0 STRUCTTYPE Descriptor Type This field indicates which type of descriptor this is It must be 1 for a SYNC descriptor 20 DONEIFSEN Done if Set indicator If set the interrupt flag will be set descriptor completes 7 0 SYNCCLR Sync Trigger Clear This bit field is used to clear corresponding bits within the SYNCTRIG field of ...

Page 109: ... LINKMODE Bit Name Description 1 0 STRUCTTYPE Descriptor Type This field indicates which type of descriptor this is It must be 2 for a WRI descriptor 20 DONEIFSEN Done if Set indicator If set the interrupt flag will be set descriptor completes 31 0 IMMVAL Immediate Value for Write This bit field specifies the immediate data value that is to be written to the address pointed to by DSTADDR Only one ...

Page 110: ...ftware writes directly to the LDMA channel registers This example does not use a memory based descriptor list This example is suitable for most simple transfers that are limited to transferring one block of data It supports anything that can be done using a single descriptor This includes endian conversion and packing unpacking data Channel 0 is used for this example The LDMA will be used to copy ...

Page 111: ...s soon as they are loaded Write 0x00000013 to the LINK member of all but the last descriptor LINKMODE 1 relative addressing LINK 1 Link to the next descriptor LINKADDR 0x00000010 size of descriptor Set the DONEIFSEN bit in the CTRL member of the 2nd structure so that the interrupt flag will be set when it completes Write 0x00000000 to the LINK member of the last descriptor LINK 0 Do not link to th...

Page 112: ...one for memory to memory Clear and enable interrupts as desired Set bit 0 in the LDMA_LINKLOAD register to initate loading and execution of the first descriptor Alternativley software can manually copy the first descriptor contents to the LDMA_CH0_CTRL LDMA_CH0_SRC LDMA_CH0_DST and LDMA_CH0_LINK registers and then enable the channel in the LDMA_CHEN register EFM32JG1 Reference Manual LDMA Linked D...

Page 113: ...p XFERCNT 4 4 words STRUCTTPYE 0 TRANSFER IGNORESREQ 1 ignore single requests Write the address ADC0_SINGLEDATA register to the SRC member Write 0x1000 address to DST member Configure the LINKLink member LINK 0 stop after loop MODE 1 relative link address LINKADDR 0 point to ourself Configure the Channel Write the desired number of repeats to the LDMA_CH0_LOOP register SOURCESEL in LDMA_CH0REQSEL ...

Page 114: ...ping Once the LOOPCNT rea ches zero the LDMA will load descriptor C Descriptor C must be located immediately following descriptor B Ctrl Src Dst Link A B Ctrl Src Dst Link Memory 0x00 0x10 link_addr B link_addr NA C Ctrl Src Dst Link 0x20 link_addr A Alternate link A B LINKADDR A DECLOOPCNT 1 C LINK 0 LINKADDR B Figure 7 7 Descriptor List with Looping Initialization is similar to the single loopin...

Page 115: ... set by a sync set clear structure which is controlled by channel 1 Sync structures do not transfer data they can only set clear or wait to match the SYNCTRIG 7 0 bits Note that sync structures cannot decrement loop counter LDMA_SYNC SYNCTRIG 0x0 at time 0 LDMA_CH0 Structure A 0x00 Structure B 0x10 Structure C 0x20 CTRL CTRL CTRL STRUCTTYPE XFER STRUCTTYPE SYNC STRUCTTYPE XFER LINK LINK LINK LINKA...

Page 116: ...oth A and Y effectively start at the same time A finishes earlier then it links to B which waits for the SYNCTRIG 7 bit to be set before loading C Y finishes after B is loaded and it links to sync structure Z which sets the SYNCTRIG 7 bit Channel 0 responds to the trigger set by loading C for the final data transfer EFM32JG1 Reference Manual LDMA Linked DMA Controller silabs com Smart Connected En...

Page 117: ...int to the desired target ad dresses The first descriptor will copy only the first row The XFERCNT of the first descriptor is set to the desired width minus one CTRL XFERCNT WIDTH 1 SRCMD 0 absolute DSTMD 0 absolute SRCADDR target source address DSTADDR target destination address LINK 0x00000013 LINK 1 LINKMD 1 LINKADDR 0x00000010 point to next descriptor The second descriptor will use relative ad...

Page 118: ...s same method is easily extended to copy multiple rectangles by linking descriptors together To initialize the LDMA_CHx_LOOP register precede each descriptor pair described above with a write immediate descriptor which writes the desired value to the LOOPCNT field of the LDMA_CHx_LOOP register EFM32JG1 Reference Manual LDMA Linked DMA Controller silabs com Smart Connected Energy friendly Prelimina...

Page 119: ...nsferring data to the second buffer For a receiver ping pong buffer each descriptor should link to the other descriptor The link bit should be set to provide infinite ping pong between the two buffers The DONIFS bit in each descriptor should be set to generate an interrupt on the completion of each descriptor Descriptor A CTRL DONEIFS 1 other settings as desired SRCADDR peripheral source address D...

Page 120: ...er Gather Scatter Gather in general refers to a process that copies data from multiple locations scattered in memory and gathers the data to a single location in memory or vice versa A simple descriptor list allows data gathering For example data from a discontiguous list of buffers might be copied to a contiguous sequential array of buffers The inverse is also possible when a sequential array of ...

Page 121: ...ster 0x084 LDMA_CH0_CFG RW Channel Configuration Register 0x088 LDMA_CH0_LOOP RWH Channel Loop Counter Register 0x08C LDMA_CH0_CTRL RWH Channel Descriptor Control Word Register 0x090 LDMA_CH0_SRC RWH Channel Descriptor Source Data Address Register 0x094 LDMA_CH0_DST RWH Channel Descriptor Destination Data Address Register 0x098 LDMA_CH0_LINK RWH Channel Descriptor Link Structure Address Register L...

Page 122: ...els Channels CH0 though CH n 1 are fixed and channels CH n through CH7 are round robin where n is the field value The reset value will give all fixed channels 23 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 15 8 SYNCPRSCLREN 0x00 RW Synchronization PRS Clear Enable Setting a bit in this field will enable the corresponding PRS i...

Page 123: ...s in the FIFO 15 11 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 10 8 CHERROR 0x0 R Errant Channel Number When the ERROR flag is set in the LDMA_IF register the CHERROR field will indicate the most recent channel to have a transfer error 7 6 Reserved To ensure compatibility with future devices always write bits to 0 More informati...

Page 124: ...le read modify write detailed in 7 6 4 LDMA_CHEN DMA Channel Enable Register Single Cycle RMW Offset Bit Position 0x020 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 Access RWH Name CHEN Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 7 0 CHEN 0...

Page 125: ...6 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 Access RWH Name CHDONE Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 7 0 CHDONE 0x00 RWH DMA Channel Linking or Done Each DMA channel sets the corresponding bit in this register when the entire transfer is done Th...

Page 126: ...CPU is halted This may be useful for debugging DMA software 7 6 8 LDMA_SWREQ DMA Channel Software Transfer Request Register Offset Bit Position 0x030 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 Access W1 Name SWREQ Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information ...

Page 127: ...annel When cleared any pending periph eral requests will be serviced 7 6 10 LDMA_REQPEND DMA Channel Requests Pending Register Offset Bit Position 0x038 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 Access R Name REQPEND Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More informat...

Page 128: ...e channel This empowers software to step through a sequence of descriptors 7 6 12 LDMA_REQCLEAR DMA Channel Request Clear Register Offset Bit Position 0x040 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 Access W1 Name REQCLEAR Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More in...

Page 129: ...cture Operation Done Interrupt Flag When a channel completes a transfer or sync operation the corresponding DONE bit is set in the LDMA_IF register 7 6 14 LDMA_IFS Interrupt Flag Set Register Offset Bit Position 0x064 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0x00 Access W1 W1 Name ERROR DONE Bit Name Reset Access Description 31 ERROR 0 W1 Set ER...

Page 130: ...E Interrupt Flag Write 1 to clear the DONE interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 7 6 16 LDMA_IEN Interrupt Enable register Offset Bit Position 0x06C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0x00 Access RW RW Name ERROR DONE Bit Name Reset Acces...

Page 131: ...Bit Position 0x080 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 0x0 Access RW RW Name SOURCESEL SIGSEL EFM32JG1 Reference Manual LDMA Linked DMA Controller silabs com Smart Connected Energy friendly Preliminary Rev 0 6 130 ...

Page 132: ...00 MSC Memory System Controller 0b110001 CRYPTO Advanced Encryption Standard Accelerator 15 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 3 0 SIGSEL 0x0 RW Signal Select Select input signal to DMA channel Value Mode Description SOURCESEL 0b000000 NONE 0bxxxx OFF Channel input selection is turned off SOURCESEL 0b000001 PRS 0b0000 ...

Page 133: ...EQ SREQ SOURCESEL 0b011000 TIMER0 0b0000 TIMER0UFOF TIMER0UFOF 0b0001 TIMER0CC0 TIMER0CC0 0b0010 TIMER0CC1 TIMER0CC1 0b0011 TIMER0CC2 TIMER0CC2 SOURCESEL 0b011001 TIMER1 0b0000 TIMER1UFOF TIMER1UFOF 0b0001 TIMER1CC0 TIMER1CC0 0b0010 TIMER1CC1 TIMER1CC1 0b0011 TIMER1CC2 TIMER1CC2 0b0100 TIMER1CC3 TIMER1CC3 SOURCESEL 0b110000 MSC 0b0000 MSCWDATA MSCWDATA SOURCESEL 0b110001 CRYPTO 0b0000 CRYPTODATA0W...

Page 134: ... Mode Description 0 POSITIVE Increment source address 1 NEGATIVE Decrement source address 19 18 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 17 16 ARBSLOTS 0x0 RW Arbitration Slot Number Select For channels using round robin arbitration this bit field is used to select the number of slots in the round robin queue Value Mode Descri...

Page 135: ...eserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 7 0 LOOPCNT 0x00 RWH Linked Structure Sequence Loop Counter This bit field specifies the number of iterations when using looping descriptors Software should write to LOOPCNT before using a looping descriptor EFM32JG1 Reference Manual LDMA Linked DMA Controller silabs com Smart Connected ...

Page 136: ...5 4 3 2 1 0 Reset 0 0 0x0 0x0 0x0 0 0 0 0 0x0 0 0x000 0 0x0 Access R R RWH RWH RWH RWH RWH RWH RWH RWH RWH RWH W1 R Name DSTMODE SRCMODE DSTINC SIZE SRCINC IGNORESREQ DECLOOPCNT REQMODE DONEIFSEN BLOCKSIZE BYTESWAP XFERCNT STRUCTREQ STRUCTTYPE EFM32JG1 Reference Manual LDMA Linked DMA Controller silabs com Smart Connected Energy friendly Preliminary Rev 0 6 135 ...

Page 137: ...mber of unit data addresses to increment the destination address after each unit of data is transferred The unit data width is controlled by the SIZE bit field and can be a byte half word or word Value Mode Description 0 ONE Increment destination address by one unit data size after each write 1 TWO Increment destination address by two unit data sizes after each write 2 FOUR Increment destination a...

Page 138: ... set or synchronized in the case of a SYNC transfer 19 16 BLOCKSIZE 0x0 RWH Block Transfer Size This bit field controls the number of unit data transfers per arbitration cycle Value Mode Description 0 UNIT1 One unit transfer per arbitration 1 UNIT2 Two unit transfers per arbitration 2 UNIT3 Three unit transfers per arbitration 3 UNIT4 Four unit transfers per arbitration 4 UNIT6 Six unit transfers ...

Page 139: ... selected 1 SYNCHRONIZE Synchronization structure type selected 2 WRITE Write immediate value structure type selected 7 6 21 LDMA_CHx_SRC Channel Descriptor Source Data Address Register Offset Bit Position 0x090 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access RWH Name SRCADDR Bit Name Reset Access Description 31 0 SRCADDR 0x00000000 RWH...

Page 140: ... Reset Access Description 31 0 DSTADDR 0x00000000 RWH Destination Data Address Writing to this register sets the destination address Reading from this register during a DMA transfer will indicate the next destination write address This value of this register is incremented or decremented with each destination write EFM32JG1 Reference Manual LDMA Linked DMA Controller silabs com Smart Connected Ene...

Page 141: ...g the initial transfer if this bit is set the DMA will load the next linked descriptor If the next linked descriptor also has this bit set the DMA will load the next linked descriptor 0 LINKMODE 0 R Link Structure Addressing Mode This field specifies the addressing mode of linked descriptors After loading a linked descriptor reading this field will indi cate the addressing mode of the loaded linke...

Page 142: ...lly low power consumption The cause of the reset may be read from a register thus providing software with information about the cause of the reset 8 1 Introduction The RMU is responsible for handling the reset functionality of the EFM32 Jade Gecko 8 2 Features Reset sources Power on Reset POR Brown out Detection BOD on the following power domains Analog Unregulated Power Domain AVDD Digital Unregu...

Page 143: ...RSTTn Debug Interface CORE CMU and Peripherals AVDDBODn RCCLR PAD_RESETn DVDDBODn AVDD EM4H EM4S Wakeup Resetn DVDD PORSTn POR DEC BOD BOD BOD DECBODn EXRST FULLRESETn EM4 Pin Wakeup cause Enable Full Reset Enable Extended Reset Enable Limited Reset CRYOTIMER LFOSC Ctrl RTCC VMON EXTENDEDRESETn SYSREQRST WDOGRST LOCKUPRST EXTRST SYSREQRST WDOGRST LOCKUPRST EXTRST LIMITEDRESETn DEBUGRESETn RMU_RSTC...

Page 144: ...of CRYOTIMER DEBUGGER and parts of CMU RMU and EMU FULL Everything reset with exception of some registers in RMU and EMU The reset sources resulting in a soft reset are Watchdog reset Lockup reset System reset request Pin reset1 1 Pin reset can be configured to be either a soft or a hard reset see 8 3 5 RESETn pin Reset for details Note LIMITED and EXTENDED resets are synchronized to HFSRCCLK If H...

Page 145: ...alidated i e can not be trusted one of the bits to the right of it does not match the table X bits are don t care Note Notice that it is possible to have multiple reset causes For example an external reset and a watchdog reset may happen simultaneous ly Table 8 2 RMU Reset Cause Register Interpretation RMU_RSTCAUSE Reset cause EM4R ST WDOG RST SYS REQR ST LOCK UPRS T EXTRS T DEC BOD DVDD BOD AVDD ...

Page 146: ... low for any reliable operation POWERONn VDD time V Unknown VPORthr Figure 8 2 RMU Power on Reset Operation 8 3 4 Brown Out Detector BOD The EFM32 Jade Gecko The BODs also include hysteresis which prevents instability in the corresponding BROWNOUTn line when the supply is crossing the VBODthr limit or the AVDD bods drops below decouple pin DEC The operation of the BOD is illustrated in Figure 8 3 ...

Page 147: ...n unrecoverable exception following the activation of the processor s built in system state protection hardware For more information about the Cortex M3 lockup conditions see the ARMv7 M Architecture Reference Manual The Lockup reset does not reset the Debug Interface unless configured as a FULL reset The Lockup reset can be configured to cause different levels of reset as determined by the LOCKUP...

Page 148: ...LKSEL CMU_LFECLKEN0 CMU_LFEPRESC0 Alternate reset for registers in EMU EMU reset levels POR BOD and hard pin reset EMU_DCDCLNVCTRL POR BOD and hard pin reset EMU_PWRCTRL EMU_DCDCCTRL EMU_DCDCMISCCTRL EMU_DCDCZDETCTRL EMU_DCDCCLIMCTRL EMU_DCDCTIMING EMU_DCDCLPVCTRL EMU_DCDCLPCTRL EMU_DCDCLNFREQCTRL EXTENDED reset EMU_VMONAVDDCTRL EMU_VMONALTAVDDCTRL EMU_VMONDVDDCTRL EMU_VMONIO0CTRL FULL reset EMU_E...

Page 149: ... 0x000 RMU_CTRL RW Control Register 0x004 RMU_RSTCAUSE R Reset Cause Register 0x008 RMU_CMD W1 Command Register 0x00C RMU_RST RW Reset Control Register 0x010 RMU_LOCK RWH Configuration Lock Register EFM32JG1 Reference Manual RMU Reset Management Unit silabs com Smart Connected Energy friendly Preliminary Rev 0 6 148 ...

Page 150: ...27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 0x4 0x2 0x2 0x4 Access RW RW RW RW RW Name RESETSTATE PINRMODE SYSRMODE LOCKUPRMODE WDOGRMODE EFM32JG1 Reference Manual RMU Reset Management Unit silabs com Smart Connected Energy friendly Preliminary Rev 0 6 149 ...

Page 151: ... Conven tions 10 8 SYSRMODE 0x2 RW Core Sysreset Reset Mode Controls the reset level for Core SYSREST reset request Value Mode Description 0 DISABLED Reset request is blocked 1 LIMITED The CRYOTIMER DEBUGGER RTCC are not reset 2 EXTENDED The CRYOTIMER DEBUGGER are not reset RTCC is reset 4 FULL The entire device is reset except some EMU and RMU registers 7 Reserved To ensure compatibility with fut...

Page 152: ...able bit in WDOG 1 LIMITED The CRYOTIMER DEBUGGER RTCC are not reset 2 EXTENDED The CRYOTIMER DEBUGGER are not reset RTCC is reset 4 FULL The entire device is reset except some EMU and RMU registers EFM32JG1 Reference Manual RMU Reset Management Unit silabs com Smart Connected Energy friendly Preliminary Rev 0 6 151 ...

Page 153: ...1 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 0 Access R R R R R R R R R Name EM4RST WDOGRST SYSREQRST LOCKUPRST EXTRST DECBOD DVDDBOD AVDDBOD PORST EFM32JG1 Reference Manual RMU Reset Management Unit silabs com Smart Connected Energy friendly Preliminary Rev 0 6 152 ...

Page 154: ... Table 8 2 RMU Reset Cause Register Interpretation on page 144 for details on how to interpret this bit 7 5 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 4 DECBOD 0 R Brown Out Detector Decouple Domain Reset Set if a regulated domain brown out detector reset has been performed Must be cleared by software Please see Table 8 2 RMU Re...

Page 155: ... tions 0 RCCLR 0 W1 Reset Cause Clear Set this bit to clear the RSTCAUSE register 8 6 4 RMU_RST Reset Control Register Offset Bit Position 0x00C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset Access Name Bit Name Reset Access Description 31 0 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions...

Page 156: ...tions 15 0 LOCKKEY 0x0000 RWH Configuration Lock Key Write any other value than the unlock code to lock RMU_CTRL and RMU_RST from editing Write the unlock code to un lock When reading the register bit 0 is set when the lock is enabled Mode Value Description Read Operation UNLOCKED 0 RMU registers are unlocked LOCKED 1 RMU registers are locked Write Operation LOCK 0 Lock RMU registers UNLOCK 0xE084...

Page 157: ... the CPU and peripherals with the highest clock frequency EM4 Shutoff Mode provides the lowest power state allowing the part to return to EM0 Active on a wakeup condition The EMU also controls the various power routing configurations internal regulators settings and voltage monitoring needed for optimal power configuration and protection 9 2 Features The primary features of the EMU are listed belo...

Page 158: ... combined state of these modules defines the required energy mode Figure 9 1 EMU Overview The EMU is available on the peripheral bus The energy management state machine controls the internal voltage regulators oscillators memories and interrupt system Events interrupts and resets can trigger the energy management state machine to return to the active state This is further described in the followin...

Page 159: ...r data Once completed the part is automatically placed back into the EM2 DeepSleep or EM3 Stop mode The Core can always request to go to EM1 Sleep with the WFI or WFE command during EM0 Active The core will be prevented from entering EM2 DeepSleep EM3 Stop EM4 Hibernate or EM4 Shutoff if Flash is programming or erasing An overview of supported energy modes and available functionality is shown in T...

Page 160: ...vailable Available Available Available Available BOD Power On Reset On On On On On On Pin Reset On On On On On On GPIO state retention On On On On On On 1 approximate time refer to datasheet 2 HFXO can be kept running in EM2 DeepSleep 3 I2C functionality limited to receive address recognition 4 ACMP functionality limited to edge interrupt 5 Must be using ULFRCO 6 Pin wakeup from selected pins The ...

Page 161: ...requency clock tree is inactive High frequency oscillator may still be enabled for fast startup Low frequency clock tree is inactive The following low frequency peripherals are available if clocked by the ULFRCO RTCC WDOG CRYOTIMER Wakeup to EM0 Active through Peripheral interrupt reset pin power on reset asynchronous pin interrupt I2C address recognition or ACMP edge interrupt RAM and register va...

Page 162: ...m options 9 3 2 2 Entry into EM2 DeepSleep or EM3 Stop Energy mode EM2 DeepSleep or EM3 Stop may be entered when all of the following conditions are true IDAC is currently not updating output Cortex M3 if present is in DEEPSLEEP state Flash Program Erase Inactive DMA done with all current requests Entry into EM2 DeepSleep and EM3 Stop can be blocked by setting the EMU_CTRL EM2BLOCK bit Note When E...

Page 163: ...eup Triggers from Low Energy Modes Peripheral Wakeup Trigger EM2 Deep Sleep EM3 Stop EM4 Hiber nate EM4 Shut off LEUART Low Energy Uart Receive transmit Yes LETIMER Any enabled interrupt Yes I2C Receive address recognition Yes Yes ACMP Any enabled edge interrupt Yes Yes PCNT Any enabled interrupt Yes Yes1 RTCC Any enabled interrupt Yes Yes Yes2 VMON Rising or falling edge on any moni tored power Y...

Page 164: ...DD and Low Voltage Digital Supply DECOUPLE Additional detail for each configuration and option is given in the following sec tions When assigning supply sources the following requirement must be adhered to VREGVDD AVDD Must be the highest voltage in the system VREGVDD DVDD VREGVDD IOVDD DVDD DECOUPLE The system boots up into a safe power state but must be immediately programmed to the desired conf...

Page 165: ...er power on firmware can configure the device to based on the external hardware configuration Note that the PWRCFG register can only be written once to a valid value and is then locked This should be done immediately out of boot to select the proper power config uration The DCDC and PWRCTRL registers will be locked until the PWRCFG register is configured DECOUPLE DVDD AVDD_0 VREGSW Main Supply VRE...

Page 166: ... the main supply IOVDD and AVDD are powered from the main supply as well VREGSW must be left disconnected in this configuration DECOUPLE DVDD AVDD VREGSW Main Supply VREGVSS IOVDD ANASW Analog Blocks DC DC DC DC Driver Bypass Switch VREGVDD OFF 0 1 Digital LDO Digital Logic FLASH VDD AVDD_1 EFM32JG1 Reference Manual EMU Energy Management Unit silabs com Smart Connected Energy friendly Preliminary ...

Page 167: ...he DC DC and shorts the Main Supply voltage directly to the DC DC output If and when sufficient voltage margin on the Main Supply returns the system can be switched back into DC DC regulation mode 9 3 5 DC to DC Interface The EFM32 Jade Gecko features a DC to DC buck converter which requires a single external inductor and a single external capacitor The converter takes the VREGVDD input voltage an...

Page 168: ...he LNFORCECCM bit in the EMU_DCDCMISCCTRL register CCM can be used to improve the DC DC converter s output transient response time to quick load current changes which minimizes voltage transients on the DC DC output Note that all references to CCM in the documentation actually refer to Forced Continuous Conduction Mode FCCM that is if the LNFORCECCM bit is set and the output load current is very l...

Page 169: ...p the bypass switch is on shorting the main supply to VDCDC In addition the system must take into consideration the maximum allowable DCDC load current Refer to datasheet for DCDC specification IOVDD must be less than or equal to AVDD 9 3 5 6 DC to DC Programming Guidelines Note Refer to Application Note AN0948 Power Configurations and DC DC for detailed information on programming the DC DC Ap pli...

Page 170: ... always running except in EM4 Shutoff and is independent from ADC temperature sensor The EMU provides the following features around temperature changes Wakeup from EM4 Hibernate on Temperature Change Interrupt from High Level Trip Interrupt from Low Level Trip 9 3 10 Registers latched in EM4 The following registers will be latched when enterring EM4 After wakeup from EM4 these registers will be re...

Page 171: ..._PWRCTRL RW Power Control Register 0x040 EMU_DCDCCTRL RW DCDC Control 0x04C EMU_DCDCMISCCTRL RW DCDC Miscellaneous Control Register 0x050 EMU_DCDCZDETCTRL RW DCDC Power Train NFET Zero Current Detector Control Register 0x054 EMU_DCDCCLIMCTRL RW DCDC Power Train PFET Current Limiter Control Register 0x05C EMU_DCDCLNVCTRL RWH DCDC Low Noise Voltage Register 0x060 EMU_DCDCTIMING RW DCDC Controller Ti...

Page 172: ...ved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 1 EM2BLOCK 0 RW Energy Mode 2 Block This bit is used to prevent the MCU from entering Energy Mode 2 or 3 0 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions EFM32JG1 Reference Manual EMU Energy Management Unit silabs com Smart Co...

Page 173: ...uture devices always write bits to 0 More information in 1 2 Conven tions 8 VMONFVDD 0 R VMON VDDFLASH Channel Indicates the status of the VDDFLASH channel of the VMON 7 5 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 4 VMONIO0 0 R VMON IOVDD0 Channel Indicates the status of the IOVDD0 channel of the VMON 3 VMONDVDD 0 R VMON DVDD C...

Page 174: ...Configuration Lock Key Write any other value than the unlock code to lock all EMU registers except the interrupt registers and regulator control registers from editing Write the unlock code to unlock When reading the register bit 0 is set when the lock is enabled Mode Value Description Read Operation UNLOCKED 0 EMU registers are unlocked LOCKED 1 EMU registers are locked Write Operation LOCK 0 Loc...

Page 175: ...down in EM23 with full access in EM01 Block 0 address range 0x20000000 0x20003FFF may nev er be powered down Value Mode Description 0 NONE None of the RAM blocks powered down 8 BLK4 Power down RAM blocks 4 and above address range 0x20006000 0x20007BFF 12 BLK3TO4 Power down RAM blocks 3 and above address range 0x20004000 0x20007BFF 14 BLK2TO4 Power down RAM blocks 2 and above address range 0x200020...

Page 176: ...en entering EM4 several registers will be latched in order to maintain constant functionality throughout EM4 Upon wakeup these registers will be reset and can have contradictory values to the latched values To ensure a seamless transi tion from EM4 to EM0 the unlatch command should be given after properly reconfiguring these latched registers The un latch command can be executed after any reset co...

Page 177: ...nter reset state when exiting EM4 2 SWUNLATCH Retention through EM4 and Wakeup software writes UNLATCH regis ter to remove retention 3 RETAINULFRCO 0 RW ULFRCO Retain during EM4S Retain the ULFRCO upon EM4S entry If set to 1 an already running ULFRCO will be retained in its running state in EM4 ULFRCO will always be retained if EM4STATE is in EM4H 2 RETAINLFXO 0 RW LFXO Retain during EM4 Retain th...

Page 178: ...set when a periodic temperature measurement is equal to or lower than this value If the low limit is changed during a temperature measurement TEMPACTIVE 1 the limit update will be delayed until the end of the temperature measurement 9 5 8 EMU_TEMP Value of last temperature measurement Offset Bit Position 0x020 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Re...

Page 179: ... R R R R R R R R R R R R R R R R Name TEMPHIGH TEMPLOW TEMP EM23WAKEUP DCDCINBYPASS DCDCLNRUNNING DCDCLPRUNNING NFETOVERCURRENTLIMIT PFETOVERCURRENTLIMIT VMONFVDDRISE VMONFVDDFALL VMONIO0RISE VMONIO0FALL VMONDVDDRISE VMONDVDDFALL VMONALTAVDDRISE VMONALTAVDDFALL VMONAVDDRISE VMONAVDDFALL EFM32JG1 Reference Manual EMU Energy Management Unit silabs com Smart Connected Energy friendly Preliminary Rev ...

Page 180: ...set once the DCDC regulator has started to run in LN mode 18 DCDCLPRUNNING 0 R LP mode is running This flag is set once the DCDC regulator has started to run in LP mode 17 NFETOVERCUR RENTLIMIT 0 R NFET current limit hit Reserved for internal use 16 PFETOVERCUR RENTLIMIT 0 R PFET current limit hit Reserved for internal use 15 VMONFVDDRISE 0 R VMON VDDFLASH Channel Rise A rising edge on VMON VDDFLA...

Page 181: ...edge on Alternate VMON AVDD channel has been detected 1 VMONAVDDRISE 0 R VMON AVDD Channel Rise A rising edge on VMON AVDD channel has been detected 0 VMONAVDDFALL 0 R VMON AVDD Channel Fall A falling edge on VMON AVDD channel has been detected EFM32JG1 Reference Manual EMU Energy Management Unit silabs com Smart Connected Energy friendly Preliminary Rev 0 6 180 ...

Page 182: ...W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 Name TEMPHIGH TEMPLOW TEMP EM23WAKEUP DCDCINBYPASS DCDCLNRUNNING DCDCLPRUNNING NFETOVERCURRENTLIMIT PFETOVERCURRENTLIMIT VMONFVDDRISE VMONFVDDFALL VMONPAVDDRISE VMONPAVDDFALL VMONIO0RISE VMONIO0FALL VMONDVDDRISE VMONDVDDFALL VMONALTAVDDRISE VMONALTAVDDFALL VMONAVDDRISE VMONAVDDFALL EFM32JG1 Reference Manual EMU Energy Management Unit silabs com Smart Connected E...

Page 183: ...et NFETOVERCURRENTLIMIT Interrupt Flag Write 1 to set the NFETOVERCURRENTLIMIT interrupt flag 16 PFETOVERCUR RENTLIMIT 0 W1 Set PFETOVERCURRENTLIMIT Interrupt Flag Write 1 to set the PFETOVERCURRENTLIMIT interrupt flag 15 VMONFVDDRISE 0 W1 Set VMONFVDDRISE Interrupt Flag Write 1 to set the VMONFVDDRISE interrupt flag 14 VMONFVDDFALL 0 W1 Set VMONFVDDFALL Interrupt Flag Write 1 to set the VMONFVDDF...

Page 184: ...upt flag 2 VMONALTAVDDFALL 0 W1 Set VMONALTAVDDFALL Interrupt Flag Write 1 to set the VMONALTAVDDFALL interrupt flag 1 VMONAVDDRISE 0 W1 Set VMONAVDDRISE Interrupt Flag Write 1 to set the VMONAVDDRISE interrupt flag 0 VMONAVDDFALL 0 W1 Set VMONAVDDFALL Interrupt Flag Write 1 to set the VMONAVDDFALL interrupt flag EFM32JG1 Reference Manual EMU Energy Management Unit silabs com Smart Connected Energ...

Page 185: ...W1 R W1 R W1 R W1 R W1 R W1 R W1 R W1 R W1 R W1 R W1 R W1 Name TEMPHIGH TEMPLOW TEMP EM23WAKEUP DCDCINBYPASS DCDCLNRUNNING DCDCLPRUNNING NFETOVERCURRENTLIMIT PFETOVERCURRENTLIMIT VMONFVDDRISE VMONFVDDFALL VMONPAVDDRISE VMONPAVDDFALL VMONIO0RISE VMONIO0FALL VMONDVDDRISE VMONDVDDFALL VMONALTAVDDRISE VMONALTAVDDFALL VMONAVDDRISE VMONAVDDFALL EFM32JG1 Reference Manual EMU Energy Management Unit silabs...

Page 186: ...C 18 DCDCLPRUNNING 0 R W1 Clear DCDCLPRUNNING Interrupt Flag Write 1 to clear the DCDCLPRUNNING interrupt flag Reading returns the value of the IF and clears the corresponding in terrupt flags This feature must be enabled globally in MSC 17 NFETOVERCUR RENTLIMIT 0 R W1 Clear NFETOVERCURRENTLIMIT Interrupt Flag Write 1 to clear the NFETOVERCURRENTLIMIT interrupt flag Reading returns the value of th...

Page 187: ...lue of the IF and clears the corresponding inter rupt flags This feature must be enabled globally in MSC 3 VMONALTAVDDRISE 0 R W1 Clear VMONALTAVDDRISE Interrupt Flag Write 1 to clear the VMONALTAVDDRISE interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 2 VMONALTAVDDFALL 0 R W1 Clear VMONALTAVDDFALL Interrup...

Page 188: ...W RW RW RW RW RW RW RW RW RW RW RW Name TEMPHIGH TEMPLOW TEMP EM23WAKEUP DCDCINBYPASS DCDCLNRUNNING DCDCLPRUNNING NFETOVERCURRENTLIMIT PFETOVERCURRENTLIMIT VMONFVDDRISE VMONFVDDFALL VMONPAVDDRISE VMONPAVDDFALL VMONIO0RISE VMONIO0FALL VMONDVDDRISE VMONDVDDFALL VMONALTAVDDRISE VMONALTAVDDFALL VMONAVDDRISE VMONAVDDFALL EFM32JG1 Reference Manual EMU Energy Management Unit silabs com Smart Connected En...

Page 189: ... 0 RW NFETOVERCURRENTLIMIT Interrupt Enable Enable disable the NFETOVERCURRENTLIMIT interrupt 16 PFETOVERCUR RENTLIMIT 0 RW PFETOVERCURRENTLIMIT Interrupt Enable Enable disable the PFETOVERCURRENTLIMIT interrupt 15 VMONFVDDRISE 0 RW VMONFVDDRISE Interrupt Enable Enable disable the VMONFVDDRISE interrupt 14 VMONFVDDFALL 0 RW VMONFVDDFALL Interrupt Enable Enable disable the VMONFVDDFALL interrupt 13...

Page 190: ...5 4 3 2 1 0 Reset 0x0000 Access RW Name LOCKKEY Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 15 0 LOCKKEY 0x0000 RW Regulator and Supply Configuration Lock Key Write any other value than the unlock code to lock all regulator control registers from editing Write the unlock code to un lock Whe...

Page 191: ...d routed to DVDD 9 5 15 EMU_PWRCTRL Power Control Register Offset Bit Position 0x03C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 Access RW Name ANASW Bit Name Reset Access Description 31 6 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 5 ANASW 0 RW Analog Switch Selection Determines ...

Page 192: ... EM3 When the DCDCMODE field is set to OFF this bit must be cleared so that the DCDC remains off Reset with POR Hard Pin Reset or BOD Reset Value Mode Description 0 EM23SW DCDC mode is according to DCDCMODE field 1 EM23LOWPOWER DCDC mode is low power 3 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 1 0 DCDCMODE 0x0 RW Regulator Mo...

Page 193: ... 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x3 0x3 0x3 0x0 0x7 0x7 0 Access RW RW RW RW RW RW RW Name LPCMPBIAS LNCLIMILIMSEL LPCLIMILIMSEL BYPLIMSEL NFETCNT PFETCNT LNFORCECCM EFM32JG1 Reference Manual EMU Energy Management Unit silabs com Smart Connected Energy friendly Preliminary Rev 0 6 192 ...

Page 194: ...lated LPCLIMILIMSEL 1 Reset with POR Hard Pin Reset or BOD reset 19 16 BYPLIMSEL 0x0 RW Current Limit In Bypass Mode Set current limit in bypass mode when BYPLIMEN equals one The limit is from 20mA to 320mA with 20mA step Reset with POR Hard Pin Reset or BOD Reset 15 12 NFETCNT 0x7 RW NFET switch number selection NFET power switch count number The selected number of switches are NFETCNT 1 This val...

Page 195: ...RCECCM 1 in LN mode The configuration of this register is calculated by the allowed average reverse current I_RMAX through the equation ZDETILIMSEL I_RMAX 40mA 1 5 2 5mA NFETCNT 1 where 40mA represents the current ripple with some margin and the factor of 1 5 ac counts for detecting error and other variations When the battery is tolerable with large reverse current it is recommended to have I_RMAX...

Page 196: ...Enable Bypass current limit enable Setting this bit limits maximum current drawn from DCDC input supply while DCDC is in BY PASS mode Reset with POR Hard Pin Reset or BOD Reset 12 10 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 9 8 CLIMBLANKDLY 0x1 RW Reserved for internal use Do not change Reserved for internal use Do not change ...

Page 197: ...ould use the emlib functions for configuring this field Reset with POR Hard Pin Reset or BOD Reset 7 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 1 LNATT 0 RW Low Noise Mode Feedback Attenuation Low noise mode feedback attenuation Customers should use the emlib functions for configuring this field Reset with POR Hard Pin Reset o...

Page 198: ... Should be programmed to 119 to ensure at least 10us Wait time BYPWAIT 1 100ns 20 ns Reset with POR Hard Pin Reset or BOD Reset 19 17 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 16 12 LNWAIT 0x1F RW Low Noise Controller Initialization wait time Low noise controller Initialization wait time Add 1 to the value Should be programmed ...

Page 199: ...ect Vref level Maximum available code is 8 b11100111 LPATT and LPVREFSEL set the output of the DCDC to 4 1 LPATT 30 LPVREF 2 2mV Customers should use the emlib functions for configuring this field Reset with POR Hard Pin Reset or BOD Reset 0 LPATT 0 RW Low power feedback attenuation Low power feedback attenuation select Customers should use the emlib functions for configuring this field Reset with...

Page 200: ...duty cycling of the bias This is to minimize DC bias Reset with POR Hard Pin Reset or BOD Reset 23 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 15 12 LPCMPHYSSEL 0x7 RW LP mode hysteresis selection User programmable hysteresis level for the low power comparator Hysteresis voltage at the output is 4 1 LPATT LPCMPHYSSEL 3 13mv Cu...

Page 201: ...LN mode RCO frequency band selection Low noise mode RCO frequency selection 0 7 3 8 95MHz approximately 0 85MHz step Reset with POR Hard Pin Re set or BOD Reset 9 5 25 EMU_DCDCSYNC DCDC Read Status Register Offset Bit Position 0x078 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 Access R Name DCDCCTRLBUSY Bit Name Reset Access Description 31 1 Reserve...

Page 202: ...THRES COARSE 0x0 RW Falling Threshold Coarse Adjust Falling threshold adjust in 200 mV steps Valid values are 0x0 1 2 V through 0xD 3 8 V Reset with SYSEXTENDEDRE SETn 11 8 FALLTHRESFINE 0x0 RW Falling Threshold Fine Adjust Falling threshold adjust in 20 mV steps Valid values are 0x0 through 0x9 Reset with SYSEXTENDEDRESETn 7 4 Reserved To ensure compatibility with future devices always write bits...

Page 203: ...W Threshold Fine Adjust Threshold adjust in 20 mV steps Valid values are 0x0 through 0x9 Reset with SYSEXTENDEDRESETn 7 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 3 FALLWU 0 RW Fall Wakeup When set a wakeup from EM4H will take place upon a falling edge Reset with SYSEXTENDEDRESETn 2 RISEWU 0 RW Rise Wakeup When set a wakeup fr...

Page 204: ...eshold Fine Adjust Threshold adjust in 20 mV steps Valid values are 0x0 through 0x9 Reset with SYSEXTENDEDRESETn 7 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 3 FALLWU 0 RW Fall Wakeup When set a wakeup from EM4H will take place upon a falling edge Reset with SYSEXTENDEDRESETn 2 RISEWU 0 RW Rise Wakeup When set a wakeup from EM...

Page 205: ...ugh 0x9 Reset with SYSEXTENDEDRESETn 7 5 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 4 RETDIS 0 RW EM4 IO0 Retention disable When set the IO0 Retention will be disabled when this IO0 voltage drops below the threshold set Reset with SYSEXTEN DEDRESETn 3 FALLWU 0 RW Fall Wakeup When set a wakeup from EM4H will take place upon a fal...

Page 206: ... capability to turn on and off the clock on an individual basis to all peripheral modules in addition to enable disable and config ure the available oscillators The high degree of flexibility enables software to minimize energy consumption in any specific application by not wasting power on peripherals and oscillators that do not need to be active 10 2 Features Multiple clock sources available 38 ...

Page 207: ...PRESC PRESC CMU_HFCOREPRESC PRESC CMU_LFBPRESC0 LEUART0 CMU_PCNTCTRL PCNTnCLKSEL Debug Trace Timeout AUXCLK WDOGCLK CMU_HFCLKSEL HF clock switch CMU_DBGCLKSEL DBG prescaler CMU_HFPRESC PRESC HFCLKLE CMU_LFACLKEN0 LETIMER0 Clock Gate LFACLKLETIMER0 prescaler CMU_LFAPRESC0 LETIMER0 HFBUSCLKDMEM CMU_HFBUSCLKEN0 GPIO HFBUSCLKGPIO Clock Gate HFBUSCLK HFBUSCLKBUSMATRIX Prescaler 2 4 CMU_HFPRESC HFCLKLEP...

Page 208: ...LFAPRESC0 LETIMER0 HFBUSCLKDMEM CMU_HFBUSCLKEN0 GPIO HFBUSCLKGPIO Clock Gate HFBUSCLK HFBUSCLKBUSMATRIX Prescaler 2 4 CMU_HFPRESC HFCLKLEPRESC HFSRCCLK prescaler HFEXPCLK CMU_HFEXPPRESC PRESC HFBUSCLKDMA CMU_HFBUSCLKEN0 DMA Clock Gate DBGCLK HFBUSCLKLE CMU_HFBUSCLKEN0 LE Clock Gate ULFRCO CRYOTIMER CRYOTIMER_CTRL OSCSEL CRYOCLK MSC Flash Programming AUX HFRCO HFXO HFSRCCLK Clock Gate LFECLK clock ...

Page 209: ...s which consists of the CPU and modules that are tightly coupled to the CPU e g the cache The prescale factor for prescaling HFCLK into HFCORECLK is set using the CMU_HFCOR EPRESC register The setting can be changed dynamically and the new setting takes effect immediately Note Note that if HFPERCLK runs faster than HFCORECLK the number of clock cycles for each bus access to peripheral modules will...

Page 210: ...cked by LFBCLK has its own prescaler setting and enable bit The prescaler settings are config ured using CMU_LFBPRESC0 and the clock enable bits can be found in CMU_LFBCLKEN0 10 3 1 7 LFECLK Low Frequency E Clock LFECLK is the selected clock for the Low Energy E Peripherals There are three selectable sources for LFECLK LFRCO LFXO and ULFRCO In addition the LFECLK can be disabled which is the defau...

Page 211: ...t and stop it The AUXHFRCO is explicitely enabled by writing a 1 to AUXHFRCOEN in CMU_OS CENCMD This explicit enabling is required when using the selecting AUXCLK for SWO operation 10 3 1 12 Debug Trace Clock The CMU selects the clock used for debug trace via the DBGCLKSEL register The user can use the AUXHFRCO or the HFCLK The selected debug trace clock will be used to run the Cortex M3 trace log...

Page 212: ...MU_OSCENCMD Via the WDOG if it is configured to use LFRCO as its clock source via the CLKSEL bitfield in WDOG_CTRL while SWOSCBLOCK is set EM3 entry EM4 entry de pending on configuration in EMU_EM4CTRL LFXO Via LFXOEN in CMU_OSCENCMD Via LFXODIS in CMU_OSCENCMD Via the WDOG if it is configured to use LFXO as its clock source via the CLKSEL bitfield in WDOG_CTRL while SWOSCBLOCK is set EM3 entry EM...

Page 213: ...LFRCO or LFXO it should not be re enabled before it has been signaled to be non ready Before entering EM4 software should check that the LFRCO or LFXO is signaled to be ready before allowing or initiating the EM4 entry if that oscillator is required in EM4 Also to guarantee latching the latest settings no control write should be ongoing upon EM4 entry as can be checked via the CMU_SYNCBUSY registe...

Page 214: ...s further explained in 10 3 2 9 Automatic HFXO Start After enabling the HFXO it should not be disabled before it has been signaled to be enabled Similarly after disabling the HFXO it should not be re enabled before it has been signaled to be non enabled Typical enable and disable sequences are as follows CMU OSCENCMD CMU_OSCENCMD_HFXOEN while CMU STATUS CMU_STATUS_HFXOENS CMU_STATUS_HFXOENS CMU OS...

Page 215: ...TRL register It can be used when waking up from EM2 when either ULFRCO LFRCO or LFXO is already running and stable In this case the HFXO ready assertion can be delayed with the number of LFECLK cycles as programmed in LFTIMEOUT The HFXO ready signal is asserted when both the TIMEOUT counter configured via the CMU_HFXOTIMEOUTCTRL register and the LFTIMEOUT counter configured via CMU_HFXOCTRL regist...

Page 216: ...eady yet the HFSRCCLK will stop for the duration of the oscilla tor start up time since the oscillator driving it is not ready This effectively stalls the Core Modules and the High Frequency Peripherals It is possible to avoid this by first enabling the target oscillator e g HFXO and then waiting for that oscillator to become ready before switching the clock source This way the system continues to...

Page 217: ...Switching from HFRCO to HFXO after HFXO is ready Switching clock source for LFACLK LFBCLK and LFECLK is done by setting the LFA LFB and LFE bitfields in CMU_LFACLKSEL CMU_LFBCLKSEL and CMU_LFECLKSEL respectively To ensure no stalls in the Low Energy Peripherals the clock source should be ready before switching to it Note To save energy remember to turn off all oscillators not in use EFM32JG1 Refer...

Page 218: ...e configurable startup state and steady state control set tings from the CMU_HFXOSTARTUPCTRL and CMU_HFXOSTEADYSTATECTRL registers Configuration is required for both the startup state and the steady state of the HFXO After reaching the steady operation state of the HFXO further optimization can option ally be performed to optimize the HFXO for noise and current consumption Optimization for noise c...

Page 219: ...D CMU_OSCENCMD_HFXODIS OFF OFF OFF PDA Peak Detection Algorithm SCO Shunt Current Optimization PEAKDETSHUNTOPTMODE AUTOCMD PEAKDETSHUNTOPTMODE AUTOCMD CMU CMD CMU_CMD_HFXOPEAKDETSTART PEAKDETSHUNTOPTMODE CMD CMU CMD CMU_CMD_HFXOSHUNTOPTSTART PEAKDETSHUNTOPTMODE CMD OFF OFF Timeout configuration from CMU HFXOTIMEOUTCTRL SHUNTOPTTIMEOUT Timeout configuration from CMU HFXOTIMEOUTCTRL PEAKDETTIMEOUT H...

Page 220: ...CTRL register before starting the HFXO For PDA to work correctly the REGISHUPPER bitfield of CMU_HFXOSTEADYSTATECTRL should be programmed to the value of the steady state REGISH 3 The PEAKDETTIMEOUT bit field in the CMU_HFXOTIMEOUTCTRL register is used to time the PDA steps and needs to be configured according to the Device Datasheet for the given crystal The PEAKDETEN bitfield of the CMU_HFXOSTEA...

Page 221: ...unable capacitance which can replace external load capacitors The TUNING bitfield of the CMU_LFXOCTRL register is used to tune the internal load capacitance connected between LFXTAL_P and ground and LFXTAL_N and ground symmetrically The capacitance range and step size information is available in the device datasheets Use the formula below to calculate the TUNING bitfield TUNING desiredTotalLoadCap...

Page 222: ...nd AUXHFRCO both contain a local prescaler which can be used in com bination with any FREQRANGE setting These prescalers allow the output clocks to be divided by 1 2 or 4 as configured in the CLKDIV bitfield 10 3 2 7 LFRCO Configuration It is possible to calibrate the LFRCO to achieve higher accuracy see the device datasheets for details on accuracy The frequency is adjusted by changing the TUNING...

Page 223: ...s counted the sampled value 1 cycles The ratio between the reference and the oscillator subject to the calibration can easily be found using top 1 and sam ple 1 Overflows of the up counter will not occur If the up counter reaches its top value before the down counter reaches 0 the up counter stays at its top value Calibration can be stopped by writing CALSTOP in CMU_CMD With this HW support it is ...

Page 224: ...bration CONT 0 TOP 0 Calibration Started 0 Down counter Up counter Up counter sampled and CALRDY interrupt flag set Sampled value available in CMU_CALCNT Up counter sampled and CALRDY interrupt flag set Sampled value available in CMU_CALCNT Figure 10 12 Continuous Calibration CONT 1 EFM32JG1 Reference Manual CMU Clock Management Unit silabs com Smart Connected Energy friendly Preliminary Rev 0 6 2...

Page 225: ...REQ bitfield in CMU_STATUS The HFXODISERR flag will not get set in that case The HFXO is only disabled by hardware upon EM2 EM3 or EM4 entry In case that AUTOSTARTSELEM0EM1 is set to 1 in EM0 EM1 irrespective of the other autostart bits the HFXO select will occur im mediately even if HFXO is not ready yet Upon wake up into EM0 EM1 this can therefore lead to a relatively long startup time as the sy...

Page 226: ...STATUS HFRCOENS CMU_HFCLKSTATUS HF HFRCO clocks status HFXO ready EM0 EM1 entry with CMU_HFXOCTRL AUTOSTARTSELEM0EM1 0 Automatic switch to HFXO and disable of HFRCO HFRCO selected EM0 EM1 Entry CMU_HFXOCTRL AUTOSTARTSELEM0EM1 0 Figure 10 14 CMU HFRCO startup selection while awaiting automatic HFXO startup selection Figure 10 15 CMU Automatic HFXO startup selection while HFRCO started selected EFM3...

Page 227: ...RESC bitfield in CMU_HFPRESC is used to control the HFCLKLE frequency This is required in case LE peripherals use HFCLKLE as clock source for LFACLK or LFECLK The required settings to ensure a valid operating frequency for LFACLK LFECLK are shown in Table 10 4 Config uration For Operating Frequencies Using HFCLKLE as LFACLK LFECLK on page 226 Before going to a high frequency make sure the register...

Page 228: ...f but it can be retained on in that state as well if needed The low frequency clocks LFACLK LFBCLK LFECLK WDOGCLK and CRYOCLK are in various power do mains and therefore their availability not only depends on the chosen clock source but also on the chosen energy mode as indicated in Table 10 5 Oscillator and clock availability in Energy Modes on page 227 Table 10 5 Oscillator and clock availabilit...

Page 229: ...OUT0 and CMUCLKOUT1 are selected via the CLKOUTSEL0 and CLKOUTSEL1 fields respectively in CMU_CTRL Note that the CLKOUTSEL0 and CLKOUTSEL1 fields are also used for selecting which clock is output onto a pin as described in 10 3 5 Clock Output on a Pin In contrast with clock output on a pin however output of a clock onto PRS does not depend on any configuration of the CMU_ROUTEPEN and CMU_ROUTELOC0...

Page 230: ...ORDY and LFXORDY can be used as wake up interrupt 10 3 11 Protection It is possible to lock the control and command registers to prevent unintended software writes to critical clock settings This is control led by the CMU_LOCK register EFM32JG1 Reference Manual CMU Clock Management Unit silabs com Smart Connected Energy friendly Preliminary Rev 0 6 229 ...

Page 231: ..._LFBCLKSEL RW Low Frequency B Clock Select Register 0x088 CMU_LFECLKSEL RW Low Frequency E Clock Select Register 0x090 CMU_STATUS R Status Register 0x094 CMU_HFCLKSTATUS R HFCLK Status Register 0x09C CMU_HFXOTRIMSTATUS R HFXO Trim Status 0x0A0 CMU_IF R Interrupt Flag Register 0x0A4 CMU_IFS W1 Interrupt Flag Set Register 0x0A8 CMU_IFC R W1 Interrupt Flag Clear Register 0x0AC CMU_IEN RW Interrupt En...

Page 232: ... EMU_CMD is set for this to take effect 0x140 CMU_SYNCBUSY R Synchronization Busy Register 0x144 CMU_FREEZE RW Freeze Register 0x150 CMU_PCNTCTRL RWH PCNT Control Register 0x15C CMU_ADCCTRL RWH ADC Control Register 0x170 CMU_ROUTEPEN RW I O Routing Pin Enable Register 0x174 CMU_ROUTELOC0 RW I O Routing Location Register 0x180 CMU_LOCK RWH Configuration Lock Register EFM32JG1 Reference Manual CMU C...

Page 233: ...0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 1 0 0x0 0x0 Access RW RW RW RW Name HFPERCLKEN WSHFLE CLKOUTSEL1 CLKOUTSEL0 EFM32JG1 Reference Manual CMU Clock Management Unit silabs com Smart Connected Energy friendly Preliminary Rev 0 6 232 ...

Page 234: ...D Disabled 1 ULFRCO ULFRCO directly from oscillator 2 LFRCO LFRCO directly from oscillator 3 LFXO LFXO directly from oscillator 6 HFXO HFXO directly from oscillator 7 HFEXPCLK HFEXPCLK 9 ULFRCOQ ULFRCO qualified 10 LFRCOQ LFRCO qualified 11 LFXOQ LFXO qualified 12 HFRCOQ HFRCO qualified 13 AUXHFRCOQ AUXHFRCO qualified 14 HFXOQ HFXO qualified 15 HFSRCCLK HFSRCCLK 4 Reserved To ensure compatibility ...

Page 235: ...alified 11 LFXOQ LFXO qualified 12 HFRCOQ HFRCO qualified 13 AUXHFRCOQ AUXHFRCO qualified 14 HFXOQ HFXO qualified 15 HFSRCCLK HFSRCCLK EFM32JG1 Reference Manual CMU Clock Management Unit silabs com Smart Connected Energy friendly Preliminary Rev 0 6 234 ...

Page 236: ...ency When changing this setting there will be no glitches on the HFRCO output hence it is safe to change this setting even while the system is running on the HFRCO Only write CMU_HFRCOCTRL when it is ready for an update as indicated by HFRCOBSY 0 in CMU_SYNCBUSY Offset Bit Position 0x010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0xB 0 0x0 1 0x2 0x0...

Page 237: ...urrent Writing this field adjusts the HFRCO comparator bias current 20 16 FREQRANGE 0x08 RWH HFRCO Frequency Range Writing this field adjusts the HFRCO frequency range 15 14 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 13 8 FINETUNING 0x1F RWH HFRCO Fine Tuning Value Writing this field adjusts the HFRCO fine tuning value Higher va...

Page 238: ... divide AUXHFRCO Clock Output Writing this field configures the AUXHFRCO clock output divider Value Mode Description 0 DIV1 Divide by 1 1 DIV2 Divide by 2 2 DIV4 Divide by 4 24 LDOHP 1 RW AUXHFRCO LDO High Power Mode Settings this bit puts the AUXHFRCO LDO in high power mode 23 21 CMPBIAS 0x2 RW AUXHFRCO Comparator Bias Current Writing this field adjusts the AUXHFRCO comparator bias current 20 16 ...

Page 239: ...cription 0 2CYCLES Timeout period of 2 cycles 1 16CYCLES Timeout period of 16 cycles 2 32CYCLES Timeout period of 32 cycles 23 19 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 18 ENDEM 1 RW Enable dynamic element matching Set to enable dynamic element matching This improves average frequency accuracy at the cost of increased jitter...

Page 240: ... 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0x0 0 0 0 0x0 Access RW RW RW RW RW RW RW Name AUTOSTARTSELEM0EM1 AUTOSTARTEM0EM1 LFTIMEOUT XTO2GND XTI2GND LOWPOWER PEAKDETSHUNTOPTMODE EFM32JG1 Reference Manual CMU Clock Management Unit silabs com Smart Connected Energy friendly Preliminary Rev 0 6 239 ...

Page 241: ...les 4 32CYCLES Timeout period of 32 cycles 5 64CYCLES Timeout period of 64 cycles 6 1KCYCLES Timeout period of 1024 cycles 7 4KCYCLES Timeout period of 4096 cycles 23 11 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 10 XTO2GND 0 RW Clamp HFXTAL_P pin to ground when HFXO oscillator is off Set to enable grounding of HFXTAL_P pin when...

Page 242: ...W Name XTIBIASEN REGLVL PEAKDETTHR Bit Name Reset Access Description 31 10 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 9 XTIBIASEN 1 RW Reserved for internal use Do not change Reserved for internal use Do not change 8 7 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tion...

Page 243: ...warm phase of the HFXO 20 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 19 11 CTUNE 0x0A0 RW Sets oscillator tuning capacitance Capacitance on HFXTAL_N and HFXTAL_P pF Ctune Cpar CTUNE 8 0 x 40fF Max Ctune 25pF CLmax 12 5pF CL DNLmax 50fF 0 6ppm 12 5ppm pF This CTUNE value is applied during the startup phase of the HFXO 10 7 Reserv...

Page 244: ...lways write bits to 0 More information in 1 2 Conven tions 19 11 CTUNE 0x155 RW Sets oscillator tuning capacitance Capacitance on HFXTAL_N and HFXTAL_P pF Ctune Cpar CTUNE 8 0 x 40fF Max Ctune 25pF CLmax 12 5pF CL DNLmax 50fF 0 6ppm 12 5ppm pF This CTUNE value is applied during the steady state phase of the HFXO as well as during the peak detection and shunt current optimization algorithms 10 7 RE...

Page 245: ... 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x2 0x6 0x6 0x6 0x7 Access RW RW RW RW RW Name SHUNTOPTTIMEOUT PEAKDETTIMEOUT RESERVED2 STEADYTIMEOUT STARTUPTIMEOUT EFM32JG1 Reference Manual CMU Clock Management Unit silabs com Smart Connected Energy friendly Preliminary Rev 0 6 244 ...

Page 246: ...nds on the chosen XTAL expected value is between 25 us and 200 us Program the desired duration measured in cycles of at least 83 ns Value Mode Description 0 2CYCLES Timeout period of 2 cycles 1 4CYCLES Timeout period of 4 cycles 2 16CYCLES Timeout period of 16 cycles 3 32CYCLES Timeout period of 32 cycles 4 256CYCLES Timeout period of 256 cycles 5 1KCYCLES Timeout period of 1024 cycles 6 2KCYCLES ...

Page 247: ...p enable wait state Wait duration depends on the chosen XTAL expected value is between 100 us and 1600 us Program the desired duration measured in cycles of at least 83 ns Value Mode Description 0 2CYCLES Timeout period of 2 cycles 1 4CYCLES Timeout period of 4 cycles 2 16CYCLES Timeout period of 16 cycles 3 32CYCLES Timeout period of 32 cycles 4 256CYCLES Timeout period of 256 cycles 5 1KCYCLES T...

Page 248: ... 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x7 0 0x0 1 0 0x2 0x0 0x00 Access RW RW RW RW RW RW RW RW Name TIMEOUT BUFCUR CUR AGC HIGHAMPL GAIN MODE TUNING EFM32JG1 Reference Manual CMU Clock Management Unit silabs com Smart Connected Energy friendly Preliminary Rev 0 6 247 ...

Page 249: ...ure devices always write bits to 0 More information in 1 2 Conven tions 17 16 CUR 0x0 RW LFXO Current Trim The default value is intended to cover all use cases and reprogramming is not recommended Do not change while LFXO is enabled 15 AGC 1 RW LFXO AGC Enable Set this bit to enable automatic gain control which limits XTAL oscillation amplitude Do not change while LFXO is enabled 14 HIGHAMPL 0 RW ...

Page 250: ...lways write bits to 0 More information in 1 2 Conven tions 6 0 TUNING 0x00 RW LFXO Internal Capacitor Array Tuning Value Writing this field adjusts the internal load capacitance connected between LFXTAL_P and ground and LFXTAL_N and ground symmetrically the higher the value the higher the capacitance the lower the frequency Only increment or decre ment by 1 LSB at a time EFM32JG1 Reference Manual ...

Page 251: ...28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 0x0 0 0x0 0x0 Access RW RW RW RW RW Name PRSDOWNSEL PRSUPSEL CONT DOWNSEL UPSEL EFM32JG1 Reference Manual CMU Clock Management Unit silabs com Smart Connected Energy friendly Preliminary Rev 0 6 250 ...

Page 252: ...o ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 19 16 PRSUPSEL 0x0 RW PRS Select for PRS Input when selected in UPSEL Select PRS input for PRS based calibration Only change when calibration circuit is off Value Mode Description 0 PRSCH0 PRS Channel 0 selected as input 1 PRSCH1 PRS Channel 1 selected as input 2 PRSCH2 PRS Channel 2 selected as ...

Page 253: ...ounter 5 AUXHFRCO Select AUXHFRCO for down counter 6 PRS Select PRS input selected by PRSDOWNSEL as down counter 3 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 2 0 UPSEL 0x0 RW Calibration Up counter Select Selects clock source for the calibration up counter Only change when calibration circuit is off Value Mode Description 0 HFXO...

Page 254: ...ess Description 31 20 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 19 0 CALCNT 0x00000 RWH Calibration Counter Write top value before calibration Read calibration result from this register when Calibration Ready flag has been set EFM32JG1 Reference Manual CMU Clock Management Unit silabs com Smart Connected Energy friendly Prelimi...

Page 255: ... the LFRCO LFRCOEN has higher priority if written simultaneously WARNING Do not disable the LFRCO if this oscillator is selected as the source for HFCLK When waking up from EM4 make sure EM4UNLATCH in EMU_CMD is set for this to take effect 6 LFRCOEN 0 W1 LFRCO Enable Enables the LFRCO When waking up from EM4 make sure EM4UNLATCH in EMU_CMD is set for this to take effect 5 AUXHFRCODIS 0 W1 AUXHFRCO...

Page 256: ...rrent Optimization Start Starts the HFXO Shunt Current Optimization and runs it one time 4 HFXOPEAKDET START 0 W1 HFXO Peak Detection Start Starts the HFXO peak detection and runs it one time 3 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 1 CALSTOP 0 W1 Calibration Stop Stops the calibration counters 0 CALSTART 0 W1 Calibration ...

Page 257: ... 6 5 4 3 2 1 0 Reset 0x0 Access W1 Name HF Bit Name Reset Access Description 31 3 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 2 0 HF 0x0 W1 HFCLK Select Selects the clock source for HFCLK Note that selecting an oscillator that is disabled will cause the system clock to stop Check the status register and confirm that oscillator is...

Page 258: ...ed as LFACLK 10 5 18 CMU_LFBCLKSEL Low Frequency B Clock Select Register Offset Bit Position 0x084 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 Access RW Name LFB Bit Name Reset Access Description 31 3 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 2 0 LFB 0x0 RW Clock Select for LF...

Page 259: ...es always write bits to 0 More information in 1 2 Conven tions 2 0 LFE 0x0 RW Clock Select for LFE Selects the clock source for LFECLK When waking up from EM4 make sure EM4UNLATCH in EMU_CMD is set for this to take effect Value Mode Description 0 DISABLED LFECLK is disabled 1 LFRCO LFRCO selected as LFECLK 2 LFXO LFXO selected as LFECLK 4 ULFRCO ULFRCO selected as LFECLK EFM32JG1 Reference Manual ...

Page 260: ...0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 Access R R R R R R R R R R R R R R R R Name HFXOREGILOW HFXOAMPLOW HFXOAMPHIGH HFXOSHUNTOPTRDY HFXOPEAKDETRDY CALRDY LFXORDY LFXOENS LFRCORDY LFRCOENS AUXHFRCORDY AUXHFRCOENS HFXORDY HFXOENS HFRCORDY HFRCOENS EFM32JG1 Reference Manual CMU Clock Management Unit silabs com Smart Connected Energy friendly Preliminary Rev 0 6 259 ...

Page 261: ...21 17 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 16 CALRDY 1 R Calibration Ready Calibration is Ready 0 when calibration is ongoing 15 10 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 9 LFXORDY 0 R LFXO Ready LFXO is enabled and start up time has exceeded 8 LFXOE...

Page 262: ...ure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 2 0 SELECTED 0x1 R HFCLK Selected Clock selected as HFCLK clock source Value Mode Description 1 HFRCO HFRCO is selected as HFCLK clock source 2 HFXO HFXO is selected as HFCLK clock source 3 LFRCO LFRCO is selected as HFCLK clock source 4 LFXO LFXO is selected as HFCLK clock source EFM32JG1 Reference M...

Page 263: ...n tions 10 7 REGISH 0xA R Value of REGISH found by automatic HFXO shunt current optimi zation algorithm Can be used as initial value for REGISH value in the CMU_HFXOSTEADYSTATECTRL register if HFXO is to be star ted again 6 0 IBTRIMXOCORE 0x00 R Value of IBTRIMXOCORE found by automatic HFXO peak detec tion algorithm Can be used as initial value for IBTRIMXOCORE in the CMU_HFXOSTEADYSTATECTRL regis...

Page 264: ...4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Access R R R R R R R R R R R R R R Name CMUERR LFTIMEOUTERR HFRCODIS HFXOSHUNTOPTRDY HFXOPEAKDETRDY HFXOAUTOSW HFXODISERR CALOF CALRDY AUXHFRCORDY LFXORDY LFRCORDY HFXORDY HFRCORDY EFM32JG1 Reference Manual CMU Clock Management Unit silabs com Smart Connected Energy friendly Preliminary Rev 0 6 263 ...

Page 265: ... selection of HFXO causes a switch of the source clock used for HFCLKSRC 8 HFXODISERR 0 R HFXO Disable Error Interrupt Flag Set when software tries to disable deselect the HFXO in case the automatic enable select reason is met The HFXO was not disabled deselected 7 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 6 CALOF 0 R Calibrati...

Page 266: ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 Name CMUERR LFTIMEOUTERR HFRCODIS HFXOSHUNTOPTRDY HFXOPEAKDETRDY HFXOPEAKDETERR HFXOAUTOSW HFXODISERR CALOF CALRDY AUXHFRCORDY LFXORDY LFRCORDY HFXORDY HFRCORDY EFM32JG1 Reference Manual CMU Clock Management Unit silabs com Smart Connected Energy friendly Preliminary Rev 0 6 265 ...

Page 267: ...terrupt Flag Write 1 to set the HFXOAUTOSW interrupt flag 8 HFXODISERR 0 W1 Set HFXODISERR Interrupt Flag Write 1 to set the HFXODISERR interrupt flag 7 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 6 CALOF 0 W1 Set CALOF Interrupt Flag Write 1 to set the CALOF interrupt flag 5 CALRDY 0 W1 Set CALRDY Interrupt Flag Write 1 to set t...

Page 268: ... 0 0 0 0 0 0 0 0 Access R W1 R W1 R W1 R W1 R W1 R W1 R W1 R W1 R W1 R W1 R W1 R W1 R W1 R W1 R W1 Name CMUERR LFTIMEOUTERR HFRCODIS HFXOSHUNTOPTRDY HFXOPEAKDETRDY HFXOPEAKDETERR HFXOAUTOSW HFXODISERR CALOF CALRDY AUXHFRCORDY LFXORDY LFRCORDY HFXORDY HFRCORDY EFM32JG1 Reference Manual CMU Clock Management Unit silabs com Smart Connected Energy friendly Preliminary Rev 0 6 267 ...

Page 269: ... W1 Clear HFXOAUTOSW Interrupt Flag Write 1 to clear the HFXOAUTOSW interrupt flag Reading returns the value of the IF and clears the corresponding inter rupt flags This feature must be enabled globally in MSC 8 HFXODISERR 0 R W1 Clear HFXODISERR Interrupt Flag Write 1 to clear the HFXODISERR interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This featu...

Page 270: ...rrupt flags This feature must be enabled globally in MSC 0 HFRCORDY 0 R W1 Clear HFRCORDY Interrupt Flag Write 1 to clear the HFRCORDY interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC EFM32JG1 Reference Manual CMU Clock Management Unit silabs com Smart Connected Energy friendly Preliminary Rev 0 6 269 ...

Page 271: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name CMUERR LFTIMEOUTERR HFRCODIS HFXOSHUNTOPTRDY HFXOPEAKDETRDY HFXOPEAKDETERR HFXOAUTOSW HFXODISERR CALOF CALRDY AUXHFRCORDY LFXORDY LFRCORDY HFXORDY HFRCORDY EFM32JG1 Reference Manual CMU Clock Management Unit silabs com Smart Connected Energy friendly Preliminary Rev 0 6 270 ...

Page 272: ...TOSW Interrupt Enable Enable disable the HFXOAUTOSW interrupt 8 HFXODISERR 0 RW HFXODISERR Interrupt Enable Enable disable the HFXODISERR interrupt 7 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 6 CALOF 0 RW CALOF Interrupt Enable Enable disable the CALOF interrupt 5 CALRDY 0 RW CALRDY Interrupt Enable Enable disable the CALRDY in...

Page 273: ... to enable the clock for GPCRC 4 LDMA 0 RW Linked Direct Memory Access Controller Clock Enable Set to enable the clock for LDMA 3 PRS 0 RW Peripheral Reflex System Clock Enable Set to enable the clock for PRS 2 GPIO 0 RW General purpose Input Output Clock Enable Set to enable the clock for GPIO 1 CRYPTO 0 RW Advanced Encryption Standard Accelerator Clock Enable Set to enable the clock for CRYPTO 0...

Page 274: ... to enable the clock for ADC0 7 I2C0 0 RW I2C 0 Clock Enable Set to enable the clock for I2C0 6 CRYOTIMER 0 RW CryoTimer Clock Enable Set to enable the clock for CRYOTIMER 5 ACMP1 0 RW Analog Comparator 1 Clock Enable Set to enable the clock for ACMP1 4 ACMP0 0 RW Analog Comparator 0 Clock Enable Set to enable the clock for ACMP0 3 USART1 0 RW Universal Synchronous Asynchronous Receiver Transmitte...

Page 275: ...Enable Set to enable the clock for LETIMER0 10 5 30 CMU_LFBCLKEN0 Low Frequency B Clock Enable Register 0 Async Reg Offset Bit Position 0x0E8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 Access RW Name LEUART0 Bit Name Reset Access Description 31 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Co...

Page 276: ...eset 0 Access RW Name RTCC Bit Name Reset Access Description 31 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 0 RTCC 0 RW Real Time Counter and Calendar Clock Enable Set to enable the clock for RTCC EFM32JG1 Reference Manual CMU Clock Management Unit silabs com Smart Connected Energy friendly Preliminary Rev 0 6 275 ...

Page 277: ...lock divider for HFCLKLE Value Mode Description 0 DIV2 HFCLKLE is HFBUSCLKLE divided by 2 1 DIV4 HFCLKLE is HFBUSCLKLE divided by 4 23 13 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 12 8 PRESC 0x00 RW HFCLK Prescaler Specifies the clock divider for HFCLK relative to HFSRCCLK Value Description PRESC Clock division factor of PRESC ...

Page 278: ... More information in 1 2 Conven tions 10 5 34 CMU_HFPERPRESC High Frequency Peripheral Clock Prescaler Register Offset Bit Position 0x10C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x000 Access RW Name PRESC Bit Name Reset Access Description 31 17 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Con...

Page 279: ...atibility with future devices always write bits to 0 More information in 1 2 Conven tions 12 8 PRESC 0x00 RW HFEXPCLK Prescaler Specifies the clock divider for HFEXPCLK relative to HFCLK Value Description PRESC Clock division factor of PRESC 1 7 0 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions EFM32JG1 Reference Manual CMU Clock Man...

Page 280: ...n 0 DIV1 LFACLKLETIMER0 LFACLK 1 DIV2 LFACLKLETIMER0 LFACLK 2 2 DIV4 LFACLKLETIMER0 LFACLK 4 3 DIV8 LFACLKLETIMER0 LFACLK 8 4 DIV16 LFACLKLETIMER0 LFACLK 16 5 DIV32 LFACLKLETIMER0 LFACLK 32 6 DIV64 LFACLKLETIMER0 LFACLK 64 7 DIV128 LFACLKLETIMER0 LFACLK 128 8 DIV256 LFACLKLETIMER0 LFACLK 256 9 DIV512 LFACLKLETIMER0 LFACLK 512 10 DIV1024 LFACLKLETIMER0 LFACLK 1024 11 DIV2048 LFACLKLETIMER0 LFACLK 2...

Page 281: ...FBCLK 4 3 DIV8 LFBCLKLEUART0 LFBCLK 8 10 5 38 CMU_LFEPRESC0 Low Frequency E Prescaler Register 0 Async Reg When waking up from EM4 make sure EM4UNLATCH in EMU_CMD is set for this to take effect Offset Bit Position 0x130 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 Access Name RTCC Bit Name Reset Access Description 31 4 Reserved To ensure compatibi...

Page 282: ...3 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 Access R R R R R R R R R R R R Name LFXOBSY HFXOBSY LFRCOVREFBSY LFRCOBSY AUXHFRCOBSY HFRCOBSY LFEPRESC0 LFECLKEN0 LFBPRESC0 LFBCLKEN0 LFAPRESC0 LFACLKEN0 EFM32JG1 Reference Manual CMU Clock Management Unit silabs com Smart Connected Energy friendly Preliminary Rev 0 6 281 ...

Page 283: ...izing new value HFXO is also BUSY when these regis ters are actively being used e g when HFXOENS 1 27 LFRCOVREFBSY 0 R LFRCO VREF Busy Used to check the synchronization status of GMCCURTUNE Value Description 0 CMU_LFRCOCTRL GMCCURTUNE bitfield is ready for update 1 CMU_LFRCOCTRL GMCCURTUNE bitfield is busy synchronizing new value 26 LFRCOBSY 0 R LFRCO Busy Used to check the synchronization status ...

Page 284: ...ty with future devices always write bits to 0 More information in 1 2 Conven tions 6 LFBPRESC0 0 R Low Frequency B Prescaler 0 Busy Used to check the synchronization status of CMU_LFBPRESC0 Value Description 0 CMU_LFBPRESC0 is ready for update 1 CMU_LFBPRESC0 is busy synchronizing new value 5 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven...

Page 285: ... 3 2 1 0 Reset 0 Access RW Name REGFREEZE Bit Name Reset Access Description 31 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 0 REGFREEZE 0 RW Register Update Freeze When set the update of the Low Frequency clock control registers is postponed until this bit is cleared Use this bit to up date several registers simultaneously Value...

Page 286: ...th future devices always write bits to 0 More information in 1 2 Conven tions 1 PCNT0CLKSEL 0 RWH PCNT0 Clock Select This bit controls which clock that is used for the PCNT Value Mode Description 0 LFACLK LFACLK is clocking PCNT0 1 PCNT0S0 External pin PCNT0_S0 is clocking PCNT0 0 PCNT0CLKEN 0 RWH PCNT0 Clock Enable This bit enables disables the clock to the PCNT EFM32JG1 Reference Manual CMU Cloc...

Page 287: ...to 0 More information in 1 2 Conven tions 5 4 ADC0CLKSEL 0x0 RWH ADC0 Clock Select This bit controls which clock is used for ADC0 in case ADCCLKMODE in ADCn_CTRL is set to ASYNC It should only be changed when ADCCLKMODE in ADCn_CTRL is set to SYNC HFXO should never be selected as clock source for ADC0 when disabling the HFXO e g because of EM2 entry Value Mode Description 0 DISABLED ADC0 is not cl...

Page 288: ...Bit Name Reset Access Description 31 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 1 CLKOUT1PEN 0 RW CLKOUT1 Pin Enable When set the CLKOUT1 pin is enabled 0 CLKOUT0PEN 0 RW CLKOUT0 Pin Enable When set the CLKOUT0 pin is enabled EFM32JG1 Reference Manual CMU Clock Management Unit silabs com Smart Connected Energy friendly Prelimi...

Page 289: ... Value Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 3 LOC3 Location 3 4 LOC4 Location 4 5 LOC5 Location 5 6 LOC6 Location 6 7 LOC7 Location 7 7 6 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 5 0 CLKOUT0LOC 0x00 RW I O Location Decides the location of the CMU CLKOUT0 Value Mode Description 0 LOC0 Location ...

Page 290: ...L CMU_HFXOCTRL1 CMU_LFXOCTRL CMU_OS CENCMD CMU_CMD CMU_DBGCLKSEL CMU_HFCLKSEL CMU_LFCLKSEL CMU_HFBUSCLKEN0 CMU_HFCOR ECLKEN0 CMU_HFPERCLKEN0 CMU_HFPRESC CMU_HFCOREPRESC CMU_HFPERPRESC CMU_HFEXP PRESC CMU_LFACLKEN0 CMU_LFBCLKEN0 CMU_LFECLKEN0 CMU_LFAPRESC0 CMU_LFBPRESC0 CMU_LFEPRESC0 CMU_ADCCTRL and CMU_PCNTCTRL from editing Write the unlock code to unlock When reading the register bit 0 is set whe...

Page 291: ...tem events 32 bit resolu tion and selectable prescaling allows the system to stay in low energy modes for long periods of time and still maintain reliable timekeeping 11 1 Introduction The Real Time Counter and Calendar RTCC contains a 32 bit counter calendar in combination with a 15 bit pre counter to allow flexi ble prescaling of the main counter The RTCC is available in all energy modes except ...

Page 292: ...ystem PRS 11 3 Functional Description The RTCC is a 32 bit up counter with three Capture Compare channels In addition the RTCC includes a 15 bit pre counter which can be used as an independent counter or to prescale the main counter An overview of the RTCC module is shown in Figure 11 1 RTCC Overview on page 291 Counter RTCC_CNT RTCC_TIME RTCC_DATE Capture Compare Channel n n 0 1 2 Capture logic n...

Page 293: ...und when it hits the value configured in RTCC_CC0_CCV The main counter of the RTCC RTCC_CNT has two modes normal mode and calendar mode In normal mode the main counter is available in RTCC_CNT and increments upon each tick given from the pre counter Refer to 11 3 1 1 Normal Mode for a description on how to configure the frequency of these ticks In calendar mode the counter value is available in RT...

Page 294: ... days DIV32 977 µs 48 days DIV64 1 95 ms 97 days DIV128 3 91 ms 194 days DIV256 7 81 ms 388 days DIV512 15 6 ms 776 days DIV1024 31 25 ms 4 2 years DIV2048 62 5 ms 8 5 years DIV4096 0 125 s 17 years DIV8192 0 25 s 34 years DIV16384 0 5 s 68 years DIV32768 1 s 136 years By default the counter will keep counting until it reaches the top value 0xFFFFFFFF before it wraps around and continues counting ...

Page 295: ...und every seventh day Automatic leap year correction extending the month of February from 28 to 29 days every fourth year is by default enabled but can be disabled by setting the LYEARCORRDIS bit in RTCC_CTRL The pseudocode for leap year correction is as follows if RTCC_DATE_YEART modulo 2 0 if RTCC_DATE_YEARU modulo 4 0 leap_year true else leap_year false else if RTCC_DATE_YEARU 2 modulo 4 0 leap...

Page 296: ...Cx_DATE in calendar mode register when an edge is detected on the selected PRS input channel The active capture edge is configured in the ICEDGE control bits In output compare mode the compare values are set by writing to the RTCC compare channel registers RTCC_CCx_CCV RTCC_CCx_TIME and RTCC_CCx_DATE in calendar mode These values will be compared to the main counter RTCC_CNT RTCC_TIME and RTCC_DAT...

Page 297: ...6 0 RTCC_PRECNT 14 0 vs RTCC_CCx_CCV RTCC_PRECNT vs RTCC_CCx_CCV 14 0 Figure 11 5 RTCC Compare in calendar mode COMPBASE CNT on page 297 illustrates how the compare events are evaluated when in calendar mode with RTCC_CCx_CTRL_COMPBASE CNT The SECU SECT MINU MINT HOURU HOURT MONTHU and MONTHT bitfields in RTCC_CCx_TIME and RTCC_CCx_DATE are compared to the corresponding bitfields in RTCC_DATE and ...

Page 298: ...1 MASKED Subject to comparison 20 21 0 Figure 11 6 RTCC Compare mask illustration COMPMASK 11 Upon a compare match the respective Capture Compare interrupt flag CCx is set Additionally the event selected by the CMOA setting is generated on the corresponding PRS output This is illustrated in Figure 11 3 RTCC Compare match and PRS output illustration on page 295 11 3 3 Interrupts and PRS Output The ...

Page 299: ...C_POWERDOWN RTCC_CCx_CTRL RTCC_CCx_CCV RTCC_CCx_TIME RTCC_CCx_DATE 11 3 6 Oscillator Failure Detection To be able to detect OSC failure the RTCC includes a security mechanism ensuring that at least three OSC cycles are detected within one period of the ULFRCO If no OSC cycles are detected the OSCFAIL interrupt flag is set OSC failure detection is enabled by set ting the OSCFDETEN bit in RTCC_CTRL ...

Page 300: ...CK RWH Configuration Lock Register 0x03C RTCC_EM4WUEN RW Wake Up Enable 0x040 RTCC_CC0_CTRL RW CC Channel Control Register 0x044 RTCC_CC0_CCV RWH Capture Compare Value Register 0x048 RTCC_CC0_TIME RWH Capture Compare Time Register 0x04C RTCC_CC0_DATE RWH Capture Compare Date Register 0x050 RTCC_CC1_CTRL RW CC Channel Control Register 0x054 RTCC_CC1_CCV RWH Capture Compare Value Register 0x058 RTCC...

Page 301: ...et Bit Position 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0x0 0 0 0 0 Access RW RW RW RW RW RW RW RW RW Name LYEARCORRDIS CNTMODE OSCFDETEN CNTTICK CNTPRESC CCV1TOP PRECCV0TOP DEBUGRUN ENABLE EFM32JG1 Reference Manual RTCC Real Time Counter and Calendar silabs com Smart Connected Energy friendly Preliminary Rev 0 6 300 ...

Page 302: ...mode Select whether the main counter should tick on RTCC_CC0_CCV 14 0 compare match with the pre counter or tick on a pre counter tap selected in CNTPRESC bitfield in the RTCC_CTRL register Value Mode Description 0 PRESC CNT register ticks according to configuration in CNTPRESC 1 CCV0MATCH CNT register ticks when PRECNT matches RTCC_CC0_CCV 14 0 11 8 CNTPRESC 0x0 RW Counter prescaler value Configu...

Page 303: ... debug mode 1 RTCC is running in debug mode 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 0 ENABLE 0 RW RTCC Enable Enable the RTCC 11 5 2 RTCC_PRECNT Pre Counter Value Register Async Reg For More information about Registers please see 4 3 Access to Low Energy Peripherals Asynchronous Registers Offset Bit Position 0x004 31 30 29 ...

Page 304: ...NTMODE CALENDAR 11 5 4 RTCC_COMBCNT Combined Pre Counter and Counter Value Register Offset Bit Position 0x00C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000 0x0000 Access R R Name CNTLSB PRECNT Bit Name Reset Access Description 31 15 CNTLSB 0x00000 R Counter Value Gives access to the 17 LSBs of the main counter CNT Register will be read as zero ...

Page 305: ...CC_CTRL_CNTMODE NORMAL 15 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 14 12 MINT 0x0 RWH Minutes tens Shows the tens part of the minute counter Register can not be written and will be read as zero when RTCC_CTRL_CNTMODE NORMAL 11 8 MINU 0x0 RWH Minutes units Shows the unit part of the minute counter Register can not be written an...

Page 306: ...unter Register can not be written and will be read as zero when RTCC_CTRL_CNTMODE NORMAL 15 13 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 12 MONTHT 0 RWH Month tens Shows the tens part of the month counter Register can not be written and will be read as zero when RTCC_CTRL_CNTMODE NORMAL 11 8 MONTHU 0x0 RWH Month units Shows the...

Page 307: ...DAYTICK 0 R Day tick Set each time the day counter increments 7 HOURTICK 0 R Hour tick Set each time the hour counter increments 6 MINTICK 0 R Minute tick Set each time the minute counter increments 5 CNTTICK 0 R Main counter tick Set each time the main counter is updated 4 OSCFAIL 0 R Oscillator failure Interrupt Flag Set when an oscillator failure has been detected 3 CC2 0 R Channel 2 Interrupt ...

Page 308: ...DAYTICK 0 W1 Set DAYTICK Interrupt Flag Write 1 to set the DAYTICK interrupt flag 7 HOURTICK 0 W1 Set HOURTICK Interrupt Flag Write 1 to set the HOURTICK interrupt flag 6 MINTICK 0 W1 Set MINTICK Interrupt Flag Write 1 to set the MINTICK interrupt flag 5 CNTTICK 0 W1 Set CNTTICK Interrupt Flag Write 1 to set the CNTTICK interrupt flag 4 OSCFAIL 0 W1 Set OSCFAIL Interrupt Flag Write 1 to set the OS...

Page 309: ...3 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 0 0 0 Access R W1 R W1 R W1 R W1 R W1 R W1 R W1 R W1 R W1 R W1 R W1 Name MONTHTICK DAYOWOF DAYTICK HOURTICK MINTICK CNTTICK OSCFAIL CC2 CC1 CC0 OF EFM32JG1 Reference Manual RTCC Real Time Counter and Calendar silabs com Smart Connected Energy friendly Preliminary Rev 0 6 308 ...

Page 310: ...ure must be enabled globally in MSC 5 CNTTICK 0 R W1 Clear CNTTICK Interrupt Flag Write 1 to clear the CNTTICK interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 4 OSCFAIL 0 R W1 Clear OSCFAIL Interrupt Flag Write 1 to clear the OSCFAIL interrupt flag Reading returns the value of the IF and clears the corresp...

Page 311: ...the DAYOWOF interrupt 8 DAYTICK 0 RW DAYTICK Interrupt Enable Enable disable the DAYTICK interrupt 7 HOURTICK 0 RW HOURTICK Interrupt Enable Enable disable the HOURTICK interrupt 6 MINTICK 0 RW MINTICK Interrupt Enable Enable disable the MINTICK interrupt 5 CNTTICK 0 RW CNTTICK Interrupt Enable Enable disable the CNTTICK interrupt 4 OSCFAIL 0 RW OSCFAIL Interrupt Enable Enable disable the OSCFAIL ...

Page 312: ...its to 0 More information in 1 2 Conven tions 0 CLRSTATUS 0 W1 Clear RTCC_STATUS register Write a 1 to clear the RTCC_STATUS register 11 5 13 RTCC_SYNCBUSY Synchronization Busy Register Offset Bit Position 0x030 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 Access R Name CMD Bit Name Reset Access Description 31 6 Reserved To ensure compatibility with...

Page 313: ...ronous Registers Offset Bit Position 0x038 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 Access RWH Name LOCKKEY Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 15 0 LOCKKEY 0x0000 RWH Configuration Lock Key Write any other value than the unl...

Page 314: ...it Name Reset Access Description 31 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 0 EM4WU 0 RW EM4 Wake up enable Write 1 to enable wake up request write 0 to disable wake up request EFM32JG1 Reference Manual RTCC Real Time Counter and Calendar silabs com Smart Connected Energy friendly Preliminary Rev 0 6 313 ...

Page 315: ...egisters Offset Bit Position 0x040 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0x00 0 0x0 0x0 0x0 0x0 Access RW RW RW RW RW RW RW Name DAYCC COMPMASK COMPBASE PRSSEL ICEDGE CMOA MODE EFM32JG1 Reference Manual RTCC Real Time Counter and Calendar silabs com Smart Connected Energy friendly Preliminary Rev 0 6 314 ...

Page 316: ...h PRECNT 10 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 9 6 PRSSEL 0x0 RW Compare Capture Channel PRS Input Channel Selection Select PRS input channel for Compare Capture channel Value Mode Description 0 PRSCH0 PRS Channel 0 selected as input 1 PRSCH1 PRS Channel 1 selected as input 2 PRSCH2 PRS Channel 2 selected as input 3 PRSC...

Page 317: ...pture channel turned off 1 INPUTCAPTURE Input capture 2 OUTPUTCOMPARE Output compare 11 5 18 RTCC_CCx_CCV Capture Compare Value Register Async Reg For More information about Registers please see 4 3 Access to Low Energy Peripherals Asynchronous Registers Offset Bit Position 0x044 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access RWH Name ...

Page 318: ...ODE NORMAL 15 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 14 12 MINT 0x0 RWH Minutes tens Shows the tens part of the Capture Compare value for minutes Register can not be written and will be read as zero when RTCC_CTRL_CNTMODE NORMAL 11 8 MINU 0x0 RWH Minutes units Shows the unit part of the Capture Compare value for minutes Regi...

Page 319: ...egister can not be written and will be read as zero when RTCC_CTRL_CNTMODE NORMAL 7 6 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 5 4 DAYT 0x0 RWH Day of month week tens Shows the tens part of the Capture Compare value for days Register can not be written and will be read as zero when RTCC_CTRL_CNTMODE NORMAL 3 0 DAYU 0x0 RWH Day...

Page 320: ... period from 9 to 256k watchdog clock cycles Individual selection to keep running or freeze when entering EM2 DeepSleep or EM3 Stop Selection to keep running or freeze when entering debug mode Selection to block the CPU from entering Energy Mode 4 Selection to block the CMU from disabling the selected watchdog clock Configurable warning interrupt at 25 50 or 75 of the timeout period Configurable w...

Page 321: ...ere is no difference between EM0 Active and EM1 Sleep The watchdog does not run in EM4 Hibernate Shutoff If EM4BLOCK in WDOGn_CTRL is set the CPU will be prevented from entering EM4 Hibernate Shutoff by software request Note If the WDOG is clocked by the LFXO or LFRCO writing the SWOSCBLOCK bit will prevent the CPU from entering EM3 Stop When running from the ULFRCO writing the SWOSCBLOCK bit will...

Page 322: ...2 WDOG Warning Window and Timeout on page 321 illustrates the warning the window and the time out interrupts Also it shows where the prs rising edge needs to happen The prs edge detection feature is discussed later Timeout period Counter value Time Watchdog clear System reset Warning Irq Legal Window PRS Event Figure 12 2 WDOG Warning Window and Timeout When the watchdog is enabled it is recommend...

Page 323: ... Timeout period Counter value Time PRS clear Timeout Irq Warning Irq Legal Window Figure 12 2 PRS Clearing WDOG 12 3 8 PRS Rising Edge Monitoring PRS channels can be used to monitor multiple processes If enabled every time the watch dog timer is cleared the PRS channels are checked and any channel which has not seen an event can trigger an interrupt Counter value Time wdog clear PRS 0 PRS 1 Time P...

Page 324: ...ronization Busy Register 0x00C WDOGn_PCH0_PRSCTRL RW PRS Control Register 0x010 WDOGn_PCH1_PRSCTRL RW PRS Control Register 0x01C WDOG_IF R Watchdog Interrupt Flags 0x020 WDOG_IFS W1 Interrupt Flag Set Register 0x024 WDOG_IFC R W1 Interrupt Flag Clear Register 0x028 WDOG_IEN RW Interrupt Enable Register EFM32JG1 Reference Manual WDOG Watchdog Timer silabs com Smart Connected Energy friendly Prelimi...

Page 325: ...on 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0x0 0x0 0x0 0xF 0 0 0 0 0 0 0 Access RW RW RW RW RW RW RW RW RW RW RW RW RW Name WDOGRSTDIS CLRSRC WINSEL WARNSEL CLKSEL PERSEL SWOSCBLOCK EM4BLOCK LOCK EM3RUN EM2RUN DEBUGRUN EN EFM32JG1 Reference Manual WDOG Watchdog Timer silabs com Smart Connected Energy friendly Preliminary Rev 0 6 324 ...

Page 326: ...limit is 25 0 of the Timeout 3 Window limit is 37 5 of the Timeout 4 Window limit is 50 0 of the Timeout 5 Window limit is 62 5 of the Timeout 6 Window limit is 75 0 of the Timeout 7 Window limit is 87 5 of the Timeout 23 18 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 17 16 WARNSEL 0x0 RW Watchdog Timeout Period Select Select wat...

Page 327: ...s 13 Timeout period of 64k watchdog clock cycles 14 Timeout period of 128k watchdog clock cycles 15 Timeout period of 256k watchdog clock cycles 7 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 6 SWOSCBLOCK 0 RW Software Oscillator Disable Block Set to disallow disabling of the selected WDOG oscillator Writing this bit to 1 will tur...

Page 328: ...n in EM3 1 Watchdog timer is running in EM3 2 EM2RUN 0 RW Energy Mode 2 Run Enable Set to keep watchdog running in EM2 Value Description 0 Watchdog timer is frozen in EM2 1 Watchdog timer is running in EM2 1 DEBUGRUN 0 RW Debug Mode Run Enable Set to keep watchdog running in debug mode Value Description 0 Watchdog timer is frozen in debug mode 1 Watchdog timer is running in debug mode 0 EN 0 RW Wa...

Page 329: ...SYNCBUSY Synchronization Busy Register Offset Bit Position 0x008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 Access R R R R Name PCH1_PRSCTRL PCH0_PRSCTRL CMD CTRL Bit Name Reset Access Description 31 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 3 PCH1_PRSCTRL 0 R PCH1_PRSC...

Page 330: ...sure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 3 0 PRSSEL 0x0 RW PRS Channel PRS Select These bits select the PRS input for the PRS channel Value Mode Description 0 PRSCH0 PRS Channel 0 selected as input 1 PRSCH1 PRS Channel 1 selected as input 2 PRSCH2 PRS Channel 2 selected as input 3 PRSCH3 PRS Channel 3 selected as input 4 PRSCH4 PRS Channel ...

Page 331: ...upt Flag Set when a wdog clear happens before a prs event has been detected on PRS channel one 3 PEM0 0 R PRS Channel Zero Event Missing Interrupt Flag Set when a wdog clear happens before a prs event has been detected on PRS channel zero 2 WIN 0 R Wdog Window Interrupt Flag Set when a wdog clear happens below the window limit value 1 WARN 0 R Wdog Warning Timeout Interrupt Flag Set when a wdog wa...

Page 332: ...its to 0 More information in 1 2 Conven tions 4 PEM1 0 W1 Set PEM1 Interrupt Flag Write 1 to set the PEM1 interrupt flag 3 PEM0 0 W1 Set PEM0 Interrupt Flag Write 1 to set the PEM0 interrupt flag 2 WIN 0 W1 Set WIN Interrupt Flag Write 1 to set the WIN interrupt flag 1 WARN 0 W1 Set WARN Interrupt Flag Write 1 to set the WARN interrupt flag 0 TOUT 0 W1 Set TOUT Interrupt Flag Write 1 to set the TO...

Page 333: ...rupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 2 WIN 0 R W1 Clear WIN Interrupt Flag Write 1 to clear the WIN interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 1 WARN 0 R W1 Clear WARN Interrupt Flag Write 1 to clear the...

Page 334: ...es always write bits to 0 More information in 1 2 Conven tions 4 PEM1 0 RW PEM1 Interrupt Enable Enable disable the PEM1 interrupt 3 PEM0 0 RW PEM0 Interrupt Enable Enable disable the PEM0 interrupt 2 WIN 0 RW WIN Interrupt Enable Enable disable the WIN interrupt 1 WARN 0 RW WARN Interrupt Enable Enable disable the WARN interrupt 0 TOUT 0 RW TOUT Interrupt Enable Enable disable the TOUT interrupt ...

Page 335: ...direct communication between different peripheral modules without involving the CPU Peripheral modules which send out Reflex signals are called producers The PRS routes these reflex signals through reflex channels to consumer peripherals which perform actions depending on the Reflex signals received The format for the Reflex signals is not given but edge triggers and other functionality can be app...

Page 336: ...are then XOR ed with the selected input from the producers to form the output signal sent to the consumers listening to the channel For example when SWLEVEL n is set if a producer produces a signal of 1 this will cause a channel output of 0 13 3 1 1 Asynchronous Mode Reflex channels can operate in two modes synchronous or asynchronous In synchronous mode reflex signals are clocked on the HFCLK and...

Page 337: ...ns running at different frequencies 13 3 1 3 Configurable PRS Logic Each PRS channel has three logic functions that can be used by themselves or in combination The selected PRS source can be AND ed with the next PRS channel output OR ed with the previous PRS channel output and inverted This is shown in Figure 13 1 PRS Overview on page 335 The order of the functions is important If OR and AND are e...

Page 338: ...ompare Clear Trigger Pulse Level Alternate Input for S0IN Level Alternate Input for S1IN Level WDOG Peripheral Watchdog Pulse LETIMER Start LETIMER Pulse Stop LETIMER Pulse Clear LETIMER Pulse RTCC Compare Capture Channel Pulse Level PRS Set Event Pulse DMA Request 0 Pulse DMA Request 1 Pulse 13 3 4 Event on PRS The PRS can be used to send events to the MCU This is very useful in combination with ...

Page 339: ...ime TIMER0 overflows one HFPERCLK cycle high pulse using PRS channel 5 Set SOURCESEL in PRS_CH5_CTRL to TIMER0 as input to PRS channel 5 Set SIGSEL in PRS_CH5_CTRL to select the overflow signal from TIMER0 Configure ADC0 with the desired conversion set up Set SINGLEPRSEN in ADC0_SINGLECTRL to 1 to enable single conversions to be started by a high PRS input signal Set SINGLEPRSSEL in ADC0_SINGLECTR...

Page 340: ...14 PRS_ROUTELOC1 RW I O Routing Location Register 0x018 PRS_ROUTELOC2 RW I O Routing Location Register 0x020 PRS_CTRL RW Control Register 0x024 PRS_DMAREQ0 RW DMA Request 0 Register 0x028 PRS_DMAREQ1 RW DMA Request 1 Register 0x030 PRS_PEEK R PRS Channel Values 0x040 PRS_CH0_CTRL RW Channel Control Register PRS_CHx_CTRL RW Channel Control Register 0x06C PRS_CH11_CTRL RW Channel Control Register EF...

Page 341: ...0 9 CH9PULSE 0 W1 Channel 9 Pulse Generation See bit 0 8 CH8PULSE 0 W1 Channel 8 Pulse Generation See bit 0 7 CH7PULSE 0 W1 Channel 7 Pulse Generation See bit 0 6 CH6PULSE 0 W1 Channel 6 Pulse Generation See bit 0 5 CH5PULSE 0 W1 Channel 5 Pulse Generation See bit 0 4 CH4PULSE 0 W1 Channel 4 Pulse Generation See bit 0 3 CH3PULSE 0 W1 Channel 3 Pulse Generation See bit 0 2 CH2PULSE 0 W1 Channel 2 P...

Page 342: ...Level See bit 0 9 CH9LEVEL 0 RW Channel 9 Software Level See bit 0 8 CH8LEVEL 0 RW Channel 8 Software Level See bit 0 7 CH7LEVEL 0 RW Channel 7 Software Level See bit 0 6 CH6LEVEL 0 RW Channel 6 Software Level See bit 0 5 CH5LEVEL 0 RW Channel 5 Software Level See bit 0 4 CH4LEVEL 0 RW Channel 4 Software Level See bit 0 3 CH3LEVEL 0 RW Channel 3 Software Level See bit 0 2 CH2LEVEL 0 RW Channel 2 S...

Page 343: ...et GPIO output from PRS channel 9 is enabled 8 CH8PEN 0 RW CH8 Pin Enable When set GPIO output from PRS channel 8 is enabled 7 CH7PEN 0 RW CH7 Pin Enable When set GPIO output from PRS channel 7 is enabled 6 CH6PEN 0 RW CH6 Pin Enable When set GPIO output from PRS channel 6 is enabled 5 CH5PEN 0 RW CH5 Pin Enable When set GPIO output from PRS channel 5 is enabled 4 CH4PEN 0 RW CH4 Pin Enable When s...

Page 344: ...30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 0x00 0x00 0x00 Access RW RW RW RW Name CH3LOC CH2LOC CH1LOC CH0LOC EFM32JG1 Reference Manual PRS Peripheral Reflex System silabs com Smart Connected Energy friendly Preliminary Rev 0 6 343 ...

Page 345: ...ation 13 14 LOC14 Location 14 23 22 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 21 16 CH2LOC 0x00 RW I O Location Decides the location of the channel I O pin Value Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 3 LOC3 Location 3 4 LOC4 Location 4 5 LOC5 Location 5 6 LOC6 Location 6 7 LOC7 Location 7 15 14 ...

Page 346: ... 1 2 Conven tions 5 0 CH0LOC 0x00 RW I O Location Decides the location of the channel I O pin Value Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 3 LOC3 Location 3 4 LOC4 Location 4 5 LOC5 Location 5 6 LOC6 Location 6 7 LOC7 Location 7 8 LOC8 Location 8 9 LOC9 Location 9 10 LOC10 Location 10 11 LOC11 Location 11 12 LOC12 Location 12 13 LOC13 Location 13 EFM32JG1 Reference ...

Page 347: ...30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 0x00 0x00 0x00 Access RW RW RW RW Name CH7LOC CH6LOC CH5LOC CH4LOC EFM32JG1 Reference Manual PRS Peripheral Reflex System silabs com Smart Connected Energy friendly Preliminary Rev 0 6 346 ...

Page 348: ...n 10 23 22 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 21 16 CH6LOC 0x00 RW I O Location Decides the location of the channel I O pin Value Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 3 LOC3 Location 3 4 LOC4 Location 4 5 LOC5 Location 5 6 LOC6 Location 6 7 LOC7 Location 7 8 LOC8 Location 8 9 LOC9 Locati...

Page 349: ...ation 2 3 LOC3 Location 3 4 LOC4 Location 4 5 LOC5 Location 5 6 LOC6 Location 6 7 6 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 5 0 CH4LOC 0x00 RW I O Location Decides the location of the channel I O pin Value Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 3 LOC3 Location 3 4 LOC4 Location 4 5 LOC5 Locatio...

Page 350: ...0 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 0x00 0x00 0x00 Access RW RW RW RW Name CH11LOC CH10LOC CH9LOC CH8LOC EFM32JG1 Reference Manual PRS Peripheral Reflex System silabs com Smart Connected Energy friendly Preliminary Rev 0 6 349 ...

Page 351: ... O Location Decides the location of the channel I O pin Value Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 3 LOC3 Location 3 4 LOC4 Location 4 5 LOC5 Location 5 15 14 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 13 8 CH9LOC 0x00 RW I O Location Decides the location of the channel I O pin Value Mode Descri...

Page 352: ...0 More information in 1 2 Conven tions 5 0 CH8LOC 0x00 RW I O Location Decides the location of the channel I O pin Value Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 3 LOC3 Location 3 4 LOC4 Location 4 5 LOC5 Location 5 6 LOC6 Location 6 7 LOC7 Location 7 8 LOC8 Location 8 9 LOC9 Location 9 10 LOC10 Location 10 EFM32JG1 Reference Manual PRS Peripheral Reflex System silabs...

Page 353: ...cription 0 PRSCH0 PRS Channel 0 selected 1 PRSCH1 PRS Channel 1 selected 2 PRSCH2 PRS Channel 2 selected 3 PRSCH3 PRS Channel 3 selected 4 PRSCH4 PRS Channel 4 selected 5 PRSCH5 PRS Channel 5 selected 6 PRSCH6 PRS Channel 6 selected 7 PRSCH7 PRS Channel 7 selected 8 PRSCH8 PRS Channel 8 selected 9 PRSCH9 PRS Channel 9 selected 10 PRSCH10 PRS Channel 10 selected 11 PRSCH11 PRS Channel 11 selected 0...

Page 354: ...DMAREQ0 write Value Mode Description 0 PRSCH0 PRS Channel 0 selected 1 PRSCH1 PRS Channel 1 selected 2 PRSCH2 PRS Channel 2 selected 3 PRSCH3 PRS Channel 3 selected 4 PRSCH4 PRS Channel 4 selected 5 PRSCH5 PRS Channel 5 selected 6 PRSCH6 PRS Channel 6 selected 7 PRSCH7 PRS Channel 7 selected 8 PRSCH8 PRS Channel 8 selected 9 PRSCH9 PRS Channel 9 selected 10 PRSCH10 PRS Channel 10 selected 11 PRSCH...

Page 355: ...DMAREQ1 write Value Mode Description 0 PRSCH0 PRS Channel 0 selected 1 PRSCH1 PRS Channel 1 selected 2 PRSCH2 PRS Channel 2 selected 3 PRSCH3 PRS Channel 3 selected 4 PRSCH4 PRS Channel 4 selected 5 PRSCH5 PRS Channel 5 selected 6 PRSCH6 PRS Channel 6 selected 7 PRSCH7 PRS Channel 7 selected 8 PRSCH8 PRS Channel 8 selected 9 PRSCH9 PRS Channel 9 selected 10 PRSCH10 PRS Channel 10 selected 11 PRSCH...

Page 356: ...9VAL 0 R Channel 9 Current Value See bit 0 8 CH8VAL 0 R Channel 8 Current Value See bit 0 7 CH7VAL 0 R Channel 7 Current Value See bit 0 6 CH6VAL 0 R Channel 6 Current Value See bit 0 5 CH5VAL 0 R Channel 5 Current Value See bit 0 4 CH4VAL 0 R Channel 4 Current Value See bit 0 3 CH3VAL 0 R Channel 3 Current Value See bit 0 2 CH2VAL 0 R Channel 2 Current Value See bit 0 1 CH1VAL 0 R Channel 1 Curre...

Page 357: ...22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0x0 0x00 0x0 Access RW RW RW RW RW RW RW RW Name ASYNC ANDNEXT ORPREV INV STRETCH EDSEL SOURCESEL SIGSEL EFM32JG1 Reference Manual PRS Peripheral Reflex System silabs com Smart Connected Energy friendly Preliminary Rev 0 6 356 ...

Page 358: ...ge detection Value Mode Description 0 OFF Signal is left as it is 1 POSEDGE A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal 2 NEGEDGE A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal 3 BOTHEDGES A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal 19 15 Reserved To ensure compatibility...

Page 359: ...S channel 0 PRSCH0 Asynchronous 0b001 PRSCH1 PRS channel 1 PRSCH1 Asynchronous 0b010 PRSCH2 PRS channel 2 PRSCH2 Asynchronous 0b011 PRSCH3 PRS channel 3 PRSCH3 Asynchronous 0b100 PRSCH4 PRS channel 4 PRSCH4 Asynchronous 0b101 PRSCH5 PRS channel 5 PRSCH5 Asynchronous 0b110 PRSCH6 PRS channel 6 PRSCH6 Asynchronous 0b111 PRSCH7 PRS channel 7 PRSCH7 Asynchronous SOURCESEL 0b0000010 PRS 0b000 PRSCH8 PR...

Page 360: ...OURCESEL 0b0011100 TIMER0 0b000 TIMER0UF Timer 0 Underflow TIMER0UF 0b001 TIMER0OF Timer 0 Overflow TIMER0OF 0b010 TIMER0CC0 Timer 0 Compare Capture 0 TIMER0CC0 0b011 TIMER0CC1 Timer 0 Compare Capture 1 TIMER0CC1 0b100 TIMER0CC2 Timer 0 Compare Capture 2 TIMER0CC2 SOURCESEL 0b0011101 TIMER1 0b000 TIMER1UF Timer 1 Underflow TIMER1UF 0b001 TIMER1OF Timer 1 Overflow TIMER1OF 0b010 TIMER1CC0 Timer 1 C...

Page 361: ...2 GPIOPIN12 Asynchronous 0b101 GPIOPIN13 GPIO pin 13 GPIOPIN13 Asynchronous 0b110 GPIOPIN14 GPIO pin 14 GPIOPIN14 Asynchronous 0b111 GPIOPIN15 GPIO pin 15 GPIOPIN15 Asynchronous SOURCESEL 0b0110100 LETIM ER0 0b000 LETIMER0CH0 LETIMER CH0 Out LETIMER0CH0 Asynchronous 0b001 LETIMER0CH1 LETIMER CH1 Out LETIMER0CH1 Asynchronous SOURCESEL 0b0110110 PCNT0 0b000 PCNT0TCC Triggered compare match PCNT0TCC ...

Page 362: ...ture encoded inputs in EM0 Active down to EM3 Stop It can run from the internal LFACLK while counting pulses on the PCNTn_S0IN pin Or alternately the PCNTn_S0IN pin may be used as an external clock source that runs both the PCNT counter and register access 14 2 Features 16 bit counter with reload register Auxiliary counter for counting a single direction Single input oversampling up down counter m...

Page 363: ...nverted so that falling edges are counted by setting the EDGE bit in the PCNTn_CTRL register If S1CDIR in the PCNTn_CTRL register is cleared PCNTn_S0IN is the only observed input in this mode The PCNTn_S0IN input is sampled by the LFACLK and the number of detected positive or negative edges on PCNTn_S0IN appears in PCNTn_CNT The counter may be configured to count down by setting the CNTDIR bit in ...

Page 364: ...uadrature decoding The externally clocked mode supports 1X quadrature decoding whereas the oversampling mode supports 1X 2X and 4X quadrature decoding These modes are described in detail in 14 3 1 4 Externally Clocked Quadrature Decoder Mode and 14 3 1 5 Oversampling Quadrature Decoder Mode EFM32JG1 Reference Manual PCNT Pulse Counter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 ...

Page 365: ...4 2 PCNT Quadrature Coding If PCNTn_S0IN leads PCNTn_S1IN in phase the direction is clockwise and if it lags in phase the direction is counter clockwise De fault behavior is illustrated by Figure 14 2 PCNT Quadrature Coding on page 364 The counter direction may be read from the DIR bit in the PCNTn_STATUS register Additionally the DIRCNG interrupt in the PCNTn_IF register is generated when a direc...

Page 366: ...ol Status S1IN posedge S1IN negedge Count Enable CNTDIR status bit 0 0 0 0 0 1 1 0 1 0 1 1 1 1 0 0 Note PCNTn_S1IN is sampled on both edges of PCNTn_S0IN EFM32JG1 Reference Manual PCNT Pulse Counter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 365 ...

Page 367: ...s PCNTn_S0IN and PCNTn_S1IN Table 14 2 PCNT OVSQUAD 1X 2X and 4X Mode Counter Control Function on page 366 outlines the increment or decrement of the counter based on the Quadrature Mode selected Note The decoding behavior of OVSQUAD1X mode is slightly different compared to EXTCLKQUAD mode also 1X mode In the EX TCLKQUAD mode the counter is updated only on the posedge of S0IN input However in the ...

Page 368: ...in the PCNTn_IF is generated when the direction change is detected When a change is detected the DIR bit in the PCNTn_STATUS register must be read to determine the new direction In the oversampling quadrature decoder modes the maximum input toggle frequency supported is 8KHz For frequencies of 8KHz and higher incorrect decoding occurs The different decoding modes and the counter updates are futher...

Page 369: ...current and previous state transition of the rotation are in the same direction These state transitions are quadrature decoder mode specific The highlighted state trasitions in Figure 14 3 PCNT State transitions for different Oversampling Quadrature Decoder Modes on page 367 are the ones considered for the different quadrature decoder modes Figure 14 7 PCNT Oversampling Quadrature Decoder with Flu...

Page 370: ...t overflow or under flow removing the problem Figure 14 8 PCNT Hysteresis behavior of Counter on page 369 illustrates the hysteresis behavior TOP TOP 2 Overflow wrap Overflow continue cnt Underflow warp underflow continue cnt COUNTER MIN VAL MAX VAL Overflow continue cnt underflow continue cnt Figure 14 8 PCNT Hysteresis behavior of Counter Given a starting value of 0 for the counter the absolute ...

Page 371: ...e value of the auxili ary counter can be read from the PCNTn_AUXCNT register Overflows on the auxiliary counter happen when the auxiliary counter passes the top value of the pulse counter configured in PCNTn_TOP In that event the AUXOF interrupt flag is set and the auxiliary counter wraps to 0 As the auxiliary counter the main counter can be configured to count only on certain events This is done ...

Page 372: ... and the PRS output from the pulse counter is set The PRS output will remain set until the next compare and clear event Triggered compare and clear is intended for use when the pulse counter is configured to count up In this mode PCNTn_CNT will not wrap to 0 when hitting PCNTn_TOP it will keep counting In addition the counter will not overflow it will rather stop counting just setting the overflow...

Page 373: ...clock The clock selection is configured by the PCNT0CLKSEL bit in the CMU_PCNTCTRL in the Clock Management Unit CMU 10 CMU Clock Management Unit The de fault clock source is the LFACLK This PCNT module may also use PCNTn_S0IN as an external clock to clock the counter EXTCLKSINGLE mode and to sample PCNTn_S1IN EXTCLKQUAD mode Setup hold and max frequency constraints for PCNTn_S0IN and PCNTn_S1IN fo...

Page 374: ... and the CNT DIR PRS output The TCC PRS is generated on compare match of TCC event The CNT OF UF combined PRS is generated when the counter overflow or under flows The CNT DIR PRS is a level PRS and indicates the current direction of count of counter CNT Note S0PRSEN S1PRSEN S0PRSSEL S1PRSSEL should only be altered when RSTEN in PCNTn_CTRL is set 14 3 10 Interrupts The interrupt generated by PCNT ...

Page 375: ...Change Interrupt DIRCNG Generation on page 374 Standard async handshake interface PCNTn_S0IN PCNTn_S1IN Interrupt X X Invalid pulse generated when the shaft changes direction n 1 n 2 n 3 n 2 PCNTn_CNT n Delay from the shaft physically changed direction until the counter direction is changed and the interrupt is generated Figure 14 13 PCNT Direction Change Interrupt DIRCNG Generation EFM32JG1 Refer...

Page 376: ... are in sync with each other Configure PCNT0 registers eg PCNT0_INPUT PCNT0_CTRL PCNT0_OVSCFG etc Wait for PCNT0_SYCNBUSY to be cleared to ensure the registers are synchronized to the asynchronous clock domain Hold PCNT0 in sw reset by setting PCNT0_CTRL_RSTEN Configure PCNT1_CTRL to EXTCLKSINLE mode with S1CDIR and CNTDIR bit set Configure INPUT to accept prs_ufof and prs_dir of PCNT0 on S0IN and...

Page 377: ...Interrupt Flag Register 0x01C PCNTn_IFS W1 Interrupt Flag Set Register 0x020 PCNTn_IFC R W1 Interrupt Flag Clear Register 0x024 PCNTn_IEN RW Interrupt Enable Register 0x02C PCNTn_ROUTELOC0 RW I O Routing Location Register 0x040 PCNTn_FREEZE RW Freeze Register 0x044 PCNTn_SYNCBUSY R Synchronization Busy Register 0x064 PCNTn_AUXCNT R Auxiliary Counter Value Register 0x068 PCNTn_INPUT RW PCNT Input R...

Page 378: ...0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0x0 0 0 0x0 0x0 0x0 0 0 0x0 0x0 0 0 0 0 0 0 0 0x0 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name TOPBHFSEL TCCPRSSEL TCCPRSPOL PRSGATEEN TCCCOMP TCCPRESC TCCMODE EDGE CNTDIR AUXCNTEV CNTEV S1CDIR HYST DEBUGHALT AUXCNTRSTEN CNTRSTEN RSTEN FILT MODE EFM32JG1 Reference Manual PCNT Pulse Counter silabs com Smart Connecte...

Page 379: ...used to trigger a compare and clear event Value Mode Description 0 RISING Rising edge on PRS trigger compare and clear event 1 FALLING Falling edge on PRS trigger compare and clear event 24 PRSGATEEN 0 RW PRS gate enable When set the clock input to the pulse counter will be gated when the selected PRS input is the inverse of TCCPRSPOL 23 22 TCCCOMP 0x0 RW Triggered compare and clear compare mode S...

Page 380: ... OVSSINGLE EXTCLKSINGLE and OVSQUAD1X 4X modes Value Mode Description 0 POS Positive edges on the PCNTn_S0IN inputs are counted in OVSSINGLE mode Does not invert PCNTn_S1IN input in OVSSINGLE and EX TCLKSINGLE modes 1 NEG Negative edges on the PCNTn_S0IN inputs are counted in OVSSIN GLE mode Inverts the PCNTn_S1IN input in OVSSINGLE and EX TCLKSINGLE modes 14 CNTDIR 0 RW Non Quadrature Mode Counte...

Page 381: ...without pending for SYNCBUSY bit 5 CNTRSTEN 0 RW Enable CNT Reset The counter CNT is asynchronously held in reset when this bit is set The reset is synchronously released two PCNT clock edges after this bit is cleared If an external clock is used the reset should be performed by setting and clearing the bit without pending for SYNCBUSY bit This action clears the counter to its reset value 4 RSTEN ...

Page 382: ...nven tions 1 LTOPBIM 0 W1 Load TOPB Immediately This bit has no effect since TOPB is not buffered and it is loaded directly into TOP 0 LCNTIM 0 W1 Load CNT Immediately Load PCNTn_TOP into PCNTn_CNT on the next counter clock cycle 14 5 3 PCNTn_STATUS Status Register Offset Bit Position 0x008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 Access R Name ...

Page 383: ... Value Register Offset Bit Position 0x010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00FF Access R Name TOP Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 15 0 TOP 0x00FF R Counter Top Value When counting down this value is reloaded into PCNTn...

Page 384: ... 0 0 0 0 0 Access R R R R R R Name OQSTERR TCC AUXOF DIRCNG OF UF Bit Name Reset Access Description 31 6 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 5 OQSTERR 0 R Oversampling Quadrature State Error Interrupt Set in the Oversampling Quardrature Mode when incorrect state transition occurs 4 TCC 0 R Triggered compare Interrupt Read...

Page 385: ...Conven tions 5 OQSTERR 0 W1 Set OQSTERR Interrupt Flag Write 1 to set the OQSTERR interrupt flag 4 TCC 0 W1 Set TCC Interrupt Flag Write 1 to set the TCC interrupt flag 3 AUXOF 0 W1 Set AUXOF Interrupt Flag Write 1 to set the AUXOF interrupt flag 2 DIRCNG 0 W1 Set DIRCNG Interrupt Flag Write 1 to set the DIRCNG interrupt flag 1 OF 0 W1 Set OF Interrupt Flag Write 1 to set the OF interrupt flag 0 U...

Page 386: ...his feature must be enabled globally in MSC 3 AUXOF 0 R W1 Clear AUXOF Interrupt Flag Write 1 to clear the AUXOF interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 2 DIRCNG 0 R W1 Clear DIRCNG Interrupt Flag Write 1 to clear the DIRCNG interrupt flag Reading returns the value of the IF and clears the correspo...

Page 387: ... information in 1 2 Conven tions 5 OQSTERR 0 RW OQSTERR Interrupt Enable Enable disable the OQSTERR interrupt 4 TCC 0 RW TCC Interrupt Enable Enable disable the TCC interrupt 3 AUXOF 0 RW AUXOF Interrupt Enable Enable disable the AUXOF interrupt 2 DIRCNG 0 RW DIRCNG Interrupt Enable Enable disable the DIRCNG interrupt 1 OF 0 RW OF Interrupt Enable Enable disable the OF interrupt 0 UF 0 RW UF Inter...

Page 388: ...t Position 0x02C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 0x00 Access RW RW Name S1INLOC S0INLOC EFM32JG1 Reference Manual PCNT Pulse Counter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 387 ...

Page 389: ...OC8 Location 8 9 LOC9 Location 9 10 LOC10 Location 10 11 LOC11 Location 11 12 LOC12 Location 12 13 LOC13 Location 13 14 LOC14 Location 14 15 LOC15 Location 15 16 LOC16 Location 16 17 LOC17 Location 17 18 LOC18 Location 18 19 LOC19 Location 19 20 LOC20 Location 20 21 LOC21 Location 21 22 LOC22 Location 22 23 LOC23 Location 23 24 LOC24 Location 24 25 LOC25 Location 25 26 LOC26 Location 26 27 LOC27 L...

Page 390: ...C8 Location 8 9 LOC9 Location 9 10 LOC10 Location 10 11 LOC11 Location 11 12 LOC12 Location 12 13 LOC13 Location 13 14 LOC14 Location 14 15 LOC15 Location 15 16 LOC16 Location 16 17 LOC17 Location 17 18 LOC18 Location 18 19 LOC19 Location 19 20 LOC20 Location 20 21 LOC21 Location 21 22 LOC22 Location 22 23 LOC23 Location 23 24 LOC24 Location 24 25 LOC25 Location 25 26 LOC26 Location 26 27 LOC27 Lo...

Page 391: ... is not updated with the new written value 14 5 13 PCNTn_SYNCBUSY Synchronization Busy Register Offset Bit Position 0x044 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 Access R R R R Name OVSCFG TOPB CMD CTRL Bit Name Reset Access Description 31 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 ...

Page 392: ...000 Access R Name AUXCNT Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 15 0 AUXCNT 0x0000 R Auxiliary Counter Value Gives read access to the auxiliary counter EFM32JG1 Reference Manual PCNT Pulse Counter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 391 ...

Page 393: ...30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0x0 0 0x0 Access RW RW RW RW Name S1PRSEN S1PRSSEL S0PRSEN S0PRSSEL EFM32JG1 Reference Manual PCNT Pulse Counter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 392 ...

Page 394: ... PRS Channel 7 selected 8 PRSCH8 PRS Channel 8 selected 9 PRSCH9 PRS Channel 9 selected 10 PRSCH10 PRS Channel 10 selected 11 PRSCH11 PRS Channel 11 selected 5 S0PRSEN 0 RW S0IN PRS Enable When set the PRS channel is selected as input to S0IN 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 3 0 S0PRSSEL 0x0 RW S0IN PRS Channel Selec...

Page 395: ...eserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 12 FLUTTERRM 0 RW Flutter Remove When set removes flutter from Quaddecoder inputs S0IN and S1IN Available only in OVSQUAD1X 4X modes 11 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 7 0 FILTLEN 0x00 RW Configure filter ...

Page 396: ...rom 10 kbit s up to 1 Mbit s Slave arbitration and timeouts are also provided to allow implementation of an SMBus compliant sys tem The interface provided to software by the I2C module allows precise control of the transmission process and highly automated transfers Automatic recognition of slave addresses is provided in all energy modes except EM4 15 2 Features True multi master capability Suppor...

Page 397: ...Register I2Cn_SDA Receive Buffer 2 level FIFO Receive Shift Register I2 C Control and Status Peripheral Bus I2Cn_SCL Pin Ctrl Symbol Generator Receive Controller Clock Generator Address Recognizer Figure 15 1 I2C Overview EFM32JG1 Reference Manual I2C Inter Integrated Circuit Interface silabs com Smart Connected Energy friendly Preliminary Rev 0 6 396 ...

Page 398: ...including other masters Both the bus lines are open drain The maximum value of the pull up resistor can be calculated as a function of the maximal rise time tr for the given bus speed and the estimated bus capacitance Cb as shown in Figure 15 3 I2C Pull up Resistor Equation on page 397 Rp max tr 0 8473 x Cb Figure 15 3 I2C Pull up Resistor Equation The maximal rise times for 100 kHz 400 kHz and 1 ...

Page 399: ...n Figure 15 4 I2C START and STOP Conditions The START and STOP conditions are easily identifiable bus events as they are the only conditions on the bus where a transition is allowed on SDA while SCL is high During the actual data transmission SDA is only allowed to change while SCL is low and must be stable while SCL is high One bit is transferred per clock pulse on the I2C bus as shown in Figure ...

Page 400: ...us transfer is unrestricted The master ends the transmission after a N ACK by sending a STOP condition on the bus After a STOP condition any master wishing to initiate a transfer on the bus can try to gain control of it If the current master wishes to make another transfer immediately after the current it can start a new transfer directly by transmitting a repeated START condition Sr instead of a ...

Page 401: ...e slave The second byte contains the eight least signifi cant bits of the slave address When a slave receives a 10 bit address it must acknowledge both the address bytes if they match the address of the slave When performing a master transmitter operation the master transmits the two address bytes and then the remaining data as shown in Figure 15 9 I2C Master Transmitter Slave Receiver with 10 bit...

Page 402: ...d be taken if while the slave is enabled the user cannot guarantee that an address match will not occur at the exact time of slave disable or slave configuration change Worst case consequences for an address match while disabling slave or changing configuration is that the slave may end up in an undefined state To reset the slave back to a known state the EN bit in I2Cn_CTRL must be reset This sho...

Page 403: ...een transmitted a new byte is loaded into the shift register if available in the transmit buffer If the transmit buffer is empty then the shift register also remains empty The TXC flag in I2Cn_STA TUS and the TXC interrupt flags in I2Cn_IF are then set signaling that the transmit shift register is out of data TXC is cleared when new data becomes available but the TXC interrupt flag must be cleared...

Page 404: ... The data can be fetched from the buffer in two ways I2Cn_RXDATA gives access to the received byte if two bytes are received then the one received first is fetched first I2Cn_RXDOUBLE makes it possible to read the two received bytes simultaneously If an attempt is made to read more bytes from the buffer than available the RXUF interrupt flag in I2Cn_IF is set to signal the underflow and the data r...

Page 405: ...diately but if the buffer is empty the master holds the I2C bus while waiting for software to write the address to the transmit buffer After the address has been transmitted a sequence of bytes can be read from or written to the slave depending on the value of the R W bit bit 0 in the address byte If the bit was cleared the master has entered a master transmitter role where it now transmits data t...

Page 406: ...on proceed Waiting for idle Idle busy 57 B3 9B 0 57 S ADDR R A N ADDR W A N DATA P Sr X Arb lost 1 97 D7 DF 9F A N A N DATA P Sr Arb lost ADDR R Arb lost ADDR match ADDR W Arb lost ADDR match ADDR X Arb lost no match 1 71 Master receiver Master transmitter Arbitration lost Slave transmitter Slave receiver 0 57 1 93 0 1 Bus state event Transmitted by self Received from slave START condition Interru...

Page 407: ...MD PSTOP is set STOP pending in I2Cn_STATUS ABORT 2 Set the ABORT command bit in I2Cn_CMD Never the transmission is abor ted CONT 3 Set the CONT command bit in I2Cn_CMD PCONT is set in I2Cn_STATUS CONT pending NACK 4 Set the NACK command bit in I2Cn_CMD PNACK is set in I2Cn_STATUS NACK pending ACK 5 Set the ACK command bit in I2Cn_CMD AUTOACK is set in I2Cn_CTRL or PACK is set in I2Cn_STATUS ACK p...

Page 408: ...he I2C bus is assumed to be busy when coming out of a reset and the BUSY flag in I2Cn_STATUS is thus set To be able to carry through master operations on the I2C bus the bus must be idle The bus goes idle when a STOP condition is detected on the bus but on buses with little activity the time before the I2C module de tects that the bus is idle can be significant There are two ways of assuring that ...

Page 409: ... STOP and then a START as soon as possible If the master wishes to make another transfer immediately after the current the preferred way is to start a new transfer directly by transmitting a repeated START instead of a STOP followed by a START This is so because if a STOP is sent out then any master wishing to initiate a transfer on the bus can try to gain control of it If a NACK was received the ...

Page 410: ...ag None 0xD7 Data transmitted ACK received ACK interrupt flag BUSHOLD interrupt flag TXDATA DATA will be sent STOP STOP will be sent Bus will be released START Repeated start condition will be sent STOP START STOP will be sent and the bus released Then a START will be sent when the bus becomes idle 0xDF Data transmitted NACK received NACK BUSHOLD inter rupt flag CONT TXDATA DATA will be sent STOP ...

Page 411: ...he ACK NACK is transmitted and the reception is ended If START in I2Cn_CMD is set alone a repea ted start condition is transmitted after the ACK NACK If STOP in I2Cn_CMD is set a stop condition is sent regardless of whether START is set If START is set in this case it is set as pending As when operating as a master transmitter arbitration can be lost as a master receiver When this happens the ARBL...

Page 412: ...ed ACK NACK START ACK NACK will be sent and then a repeated start condition ACK NACK STOP START ACK NACK will be sent and the bus will be re leased Then a START will be sent when the bus becomes idle Stop received MSTOP interrupt flag None START START will be sent when bus becomes idle Arbitration lost ARBLOST interrupt flag None START START will be sent when bus becomes idle EFM32JG1 Reference Ma...

Page 413: ... Status Bit Description BUSY Set whenever there is activity on the bus Whether or not this module is responsible for the activity cannot be determined by this byte MASTER Set when operating as a master Cleared at all other times TRANSMITTER Set when operating as a transmitter either a master transmitter or a slave transmitter Cleared at all other times BUSHOLD Set when the bus is held by this I2C ...

Page 414: ... addressed with is defined in the I2Cn_SADDR register In addition to the address a mask must be specified telling the address comparator which bits of an incoming address to compare with the ad dress defined in I2Cn_SADDR The mask is defined in I2Cn_SADDRMASK and for every zero in the mask the corresponding bit in the slave address is treated as a don t care i e the 0 masked bits are ignored An in...

Page 415: ...rd I2C howev er If the master responds with an ACK it may expect another byte of data and data should be made available in the transmit buffer If data is not available the bus is held until data is available If the response is a NACK however this is an indication of that the master has received enough bytes and wishes to end the transmis sion The slave now automatically goes idle unless CONT in I2...

Page 416: ...DATA will be transmitted Stop received SSTOP interrupt flag None The slave goes idle START START will be sent when bus becomes idle Arbitration lost ARBLOST interrupt flag None The slave goes idle START START will be sent when the bus becomes idle EFM32JG1 Reference Manual I2C Inter Integrated Circuit Interface silabs com Smart Connected Energy friendly Preliminary Rev 0 6 415 ...

Page 417: ...ave is participating in the transmission or not as long as SLAVE in I2Cn_CTRL is set and a STOP condition is detected If arbitration is lost at any time during transmission the ARBLOST interrupt flag in I2Cn_IF is set the bus is released and the slave goes idle See Table 15 8 I2C Slave Receiver on page 416 for more information Table 15 8 I2C Slave Receiver I2Cn_STATE Description I2Cn_IF Required i...

Page 418: ...K it When the master is operating as a master transmitter the data bytes will follow after the second address byte When the master is operating as a master receiver however a repeated START condition is sent after the second address byte The address sent after this repeated START is equal to the first of the address bytes transmitted previously but now with the R W byte set and only the slave that...

Page 419: ...ransmission of a general call address i e during the transmission of the STOP condition which should never happen during normal operation this is a good indication of SDA lockup Detection of SCL lockups can be done using the timeout functionality defined in 15 3 12 6 Clock Low Timeout 15 3 12 5 Bus Idle Timeout When SCL has been high for a significant amount of time this is a good indication of th...

Page 420: ...usly to the transmit buffer using the DMA DMA_USEBURSTS needs to be set to 1 for the selected DMA channel This ensures that the transfer is made to the transmit buffer only when both buffer elements are empty For performing a DMA write to the I2Cn_TXDATA register DMA_USEBURSTC needs to be set to 1 for the selected DMA channel This ensures that a DMA transfer is made even when the transmit buffer i...

Page 421: ...ve Buffer Double Data Register 0x024 I2Cn_RXDATAP R Receive Buffer Data Peek Register 0x028 I2Cn_RXDOUBLEP R Receive Buffer Double Data Peek Register 0x02C I2Cn_TXDATA W Transmit Buffer Data Register 0x030 I2Cn_TXDOUBLE W Transmit Buffer Double Data Register 0x034 I2Cn_IF R Interrupt Flag Register 0x038 I2Cn_IFS W1 Interrupt Flag Set Register 0x03C I2Cn_IFC R W1 Interrupt Flag Clear Register 0x040...

Page 422: ...7 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 0 0x0 0x0 0 0 0 0 0 0 0 0 Access RW RW RW RW RW RW RW RW RW RW RW RW Name CLTO GIBITO BITO CLHR TXBIL GCAMEN ARBDIS AUTOSN AUTOSE AUTOACK SLAVE EN EFM32JG1 Reference Manual I2C Inter Integrated Circuit Interface silabs com Smart Connected Energy friendly Preliminary Rev 0 6 421 ...

Page 423: ...fect on the bus state 1 A bus idle timeout tells the I2C module that the bus is idle allowing new transfers to be initiated 14 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 13 12 BITO 0x0 RW Bus Idle Timeout Use to generate a timeout when SCL has been high for a given amount time between a START and STOP condition When in a bus tra...

Page 424: ...pty 1 HALFFULL TXBL status and the TXBL interrupt flag are set when the transmit buf fer goes from full to half full or empty TXBL is cleared when the buffer becomes full 6 GCAMEN 0 RW General Call Address Match Enable Set to enable address match on general call in addition to the programmed slave address Value Description 0 General call address will be NACK ed if it is not included by the slave a...

Page 425: ...nsmitted on the I2C bus 1 Addresses that are not automatically NACK ed and all data is automat ically acknowledged 1 SLAVE 0 RW Addressable as Slave Set this bit to allow the device to be selected as an I2C slave Value Description 0 All addresses will be responded to with a NACK 1 Addresses matching the programmed slave address or the general call address if enabled require a response from softwar...

Page 426: ...fore aborting the transmission The stop condition is subject to clock synchronization 4 CONT 0 W1 Continue transmission Set to continue transmission after a NACK has been received 3 NACK 0 W1 Send NACK Set to transmit a NACK the next time an acknowledge is required 2 ACK 0 W1 Send ACK Set to transmit an ACK the next time an acknowledge is required 1 STOP 0 W1 Send stop condition Set to send stop c...

Page 427: ... received 6 DATAACK Data ack nack transmitted or received 4 BUSHOLD 0 R Bus Held Set if the bus is currently being held by this I2C module 3 NACKED 0 R Nack Received Set if a NACK was received and STATE is ADDRACK or DATAACK 2 TRANSMITTER 0 R Transmitter Set when operating as a master transmitter or a slave transmitter When cleared the system may be operating as a master receiver a slave receiver ...

Page 428: ...Indicates the level of the transmit buffer Set when the transmit buffer is empty and cleared when it is full 6 TXC 0 R TX Complete Set when a transmission has completed and no more data is available in the transmit buffer Cleared when a new transmis sion starts 5 PABORT 0 R Pending abort An abort is pending and will be transmitted as soon as possible 4 PCONT 0 R Pending continue A continue is pend...

Page 429: ...abled 15 5 6 I2Cn_SADDR Slave Address Register Offset Bit Position 0x014 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 Access RW Name ADDR Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 7 1 ADDR 0x00 RW Slave address Specifies the slave address...

Page 430: ...ress specified by ADDR 0 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 15 5 8 I2Cn_RXDATA Receive Buffer Data Register Actionable Reads Offset Bit Position 0x01C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 Access R Name RXDATA Bit Name Reset Access Description 31 8 Reserved To en...

Page 431: ...DATA0 0x00 R RX Data 0 First byte read from buffer Buffer is emptied on read access 15 5 10 I2Cn_RXDATAP Receive Buffer Data Peek Register Offset Bit Position 0x024 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 Access R Name RXDATAP Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 M...

Page 432: ...ead access 7 0 RXDATAP0 0x00 R RX Data 0 Peek First byte read from buffer Buffer is not emptied on read access 15 5 12 I2Cn_TXDATA Transmit Buffer Data Register Offset Bit Position 0x02C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 Access W Name TXDATA Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices alw...

Page 433: ...1 TXDATA0 Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 15 8 TXDATA1 0x00 W TX Data Second byte to write to buffer 7 0 TXDATA0 0x00 W TX Data First byte to write to buffer EFM32JG1 Reference Manual I2C Inter Integrated Circuit Interface silabs com Smart Connected Energy friendly Preliminary R...

Page 434: ...3 2 1 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Access R R R R R R R R R R R R R R R R R R R Name CLERR RXFULL SSTOP CLTO BITO RXUF TXOF BUSHOLD BUSERR ARBLOST MSTOP NACK ACK RXDATAV TXBL TXC ADDR RSTART START EFM32JG1 Reference Manual I2C Inter Integrated Circuit Interface silabs com Smart Connected Energy friendly Preliminary Rev 0 6 433 ...

Page 435: ...R Bus Held Interrupt Flag Set when the bus becomes held by the I2C module 10 BUSERR 0 R Bus Error Interrupt Flag Set when a bus error is detected The bus error is resolved automatically but the current transfer is aborted 9 ARBLOST 0 R Arbitration Lost Interrupt Flag Set when arbitration is lost 8 MSTOP 0 R Master STOP Condition Interrupt Flag Set when a STOP condition has been successfully transm...

Page 436: ...tart condition is detected 0 START 0 R START condition Interrupt Flag Set when a start condition is successfully transmitted EFM32JG1 Reference Manual I2C Inter Integrated Circuit Interface silabs com Smart Connected Energy friendly Preliminary Rev 0 6 435 ...

Page 437: ... 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 Name CLERR RXFULL SSTOP CLTO BITO RXUF TXOF BUSHOLD BUSERR ARBLOST MSTOP NACK ACK TXC ADDR RSTART START EFM32JG1 Reference Manual I2C Inter Integrated Circuit Interface silabs com Smart Connected Energy friendly Preliminary Rev 0 6 436 ...

Page 438: ...OLD interrupt flag 10 BUSERR 0 W1 Set BUSERR Interrupt Flag Write 1 to set the BUSERR interrupt flag 9 ARBLOST 0 W1 Set ARBLOST Interrupt Flag Write 1 to set the ARBLOST interrupt flag 8 MSTOP 0 W1 Set MSTOP Interrupt Flag Write 1 to set the MSTOP interrupt flag 7 NACK 0 W1 Set NACK Interrupt Flag Write 1 to set the NACK interrupt flag 6 ACK 0 W1 Set ACK Interrupt Flag Write 1 to set the ACK inter...

Page 439: ...et 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access R W1 R W1 R W1 R W1 R W1 R W1 R W1 R W1 R W1 R W1 R W1 R W1 R W1 R W1 R W1 R W1 R W1 Name CLERR RXFULL SSTOP CLTO BITO RXUF TXOF BUSHOLD BUSERR ARBLOST MSTOP NACK ACK TXC ADDR RSTART START EFM32JG1 Reference Manual I2C Inter Integrated Circuit Interface silabs com Smart Connected Energy friendly Preliminary Rev 0 6 438 ...

Page 440: ...pt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 11 BUSHOLD 0 R W1 Clear BUSHOLD Interrupt Flag Write 1 to clear the BUSHOLD interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 10 BUSERR 0 R W1 Clear BUSERR Interrupt Flag Writ...

Page 441: ...be enabled globally in MSC 1 RSTART 0 R W1 Clear RSTART Interrupt Flag Write 1 to clear the RSTART interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 0 START 0 R W1 Clear START Interrupt Flag Write 1 to clear the START interrupt flag Reading returns the value of the IF and clears the corresponding interrupt f...

Page 442: ...Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name CLERR RXFULL SSTOP CLTO BITO RXUF TXOF BUSHOLD BUSERR ARBLOST MSTOP NACK ACK RXDATAV TXBL TXC ADDR RSTART START EFM32JG1 Reference Manual I2C Inter Integrated Circuit Interface silabs com Smart Connected Energy friendly Preliminary Rev 0 6 441 ...

Page 443: ...Enable Enable disable the BUSHOLD interrupt 10 BUSERR 0 RW BUSERR Interrupt Enable Enable disable the BUSERR interrupt 9 ARBLOST 0 RW ARBLOST Interrupt Enable Enable disable the ARBLOST interrupt 8 MSTOP 0 RW MSTOP Interrupt Enable Enable disable the MSTOP interrupt 7 NACK 0 RW NACK Interrupt Enable Enable disable the NACK interrupt 6 ACK 0 RW ACK Interrupt Enable Enable disable the ACK interrupt ...

Page 444: ...0 Reset 0 0 Access RW RW Name SCLPEN SDAPEN Bit Name Reset Access Description 31 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 1 SCLPEN 0 RW SCL Pin Enable When set the SCL pin of the I2C is enabled 0 SDAPEN 0 RW SDA Pin Enable When set the SDA pin of the I2C is enabled EFM32JG1 Reference Manual I2C Inter Integrated Circuit Inter...

Page 445: ...n 0x048 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 0x00 Access RW RW Name SCLLOC SDALOC EFM32JG1 Reference Manual I2C Inter Integrated Circuit Interface silabs com Smart Connected Energy friendly Preliminary Rev 0 6 444 ...

Page 446: ... 9 LOC9 Location 9 10 LOC10 Location 10 11 LOC11 Location 11 12 LOC12 Location 12 13 LOC13 Location 13 14 LOC14 Location 14 15 LOC15 Location 15 16 LOC16 Location 16 17 LOC17 Location 17 18 LOC18 Location 18 19 LOC19 Location 19 20 LOC20 Location 20 21 LOC21 Location 21 22 LOC22 Location 22 23 LOC23 Location 23 24 LOC24 Location 24 25 LOC25 Location 25 26 LOC26 Location 26 27 LOC27 Location 27 28 ...

Page 447: ... LOC9 Location 9 10 LOC10 Location 10 11 LOC11 Location 11 12 LOC12 Location 12 13 LOC13 Location 13 14 LOC14 Location 14 15 LOC15 Location 15 16 LOC16 Location 16 17 LOC17 Location 17 18 LOC18 Location 18 19 LOC19 Location 19 20 LOC20 Location 20 21 LOC21 Location 21 22 LOC22 Location 22 23 LOC23 Location 23 24 LOC24 Location 24 25 LOC25 Location 25 26 LOC26 Location 26 27 LOC27 Location 27 28 LO...

Page 448: ...sor mode allows the USART to remain idle when not addressed Triple buffering and DMA sup port makes high data rates possible with minimal CPU intervention and it is possible to transmit and receive large frames while the MCU remains in EM1 Sleep 16 1 Introduction The Universal Synchronous Asynchronous serial Receiver and Transmitter USART is a very flexible serial I O module It supports full duple...

Page 449: ...ynchronous mode supports All 4 SPI clock polarity phase configurations Master and slave mode Data can be transmitted LSB first or MSB first Configurable number of data bits 4 16 plus the parity bit if enabled HW parity bit generation and check Configurable number of stop bits in asynchronous mode 0 5 1 1 5 2 HW collision detection Multi processor mode IrDA modulator on USART0 SmartCard ISO7816 mod...

Page 450: ...ster UART Control and status Peripheral Bus Baud rate generator USn_CLK Pin ctrl USn_CS U S n_RX IrDA modulator IrDA demodulator RXBLOCK PRS inputs USn_CTS USn_RTS TIMECMP2 Timer TIMECMP1 TIMECMP0 Auto Baud Detection Figure 16 1 USART Overview EFM32JG1 Reference Manual USART Universal Synchronous Asynchronous Receiver Transmitter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 449 ...

Page 451: ...ull duplex and half duplex communication is sup ported in both asynchronous and synchronous mode Table 16 1 USART Asynchronous vs Synchronous Mode SYNC Communication Mode Supported Protocols 0 Asynchronous RS 232 RS 485 w external driver IrDA ISO 7816 1 Synchronous SPI MicroWire 3 wire Table 16 2 USART Pin Usage on page 450 explains the functionality of the different USART pins when the USART oper...

Page 452: ...e number of data bits in a frame is set by DATABITS in USARTn_FRAME see Table 16 3 USART Data Bits on page 451 and the number of stop bits is set by STOPBITS in USARTn_FRAME see Table 16 4 USART Stop Bits on page 451 Whether or not a parity bit should be included and whether it should be even or odd is defined by PARITY also in USARTn_FRAME For communication to be possible all parties of an asynch...

Page 453: ...g When parity bits are enabled hardware automatically calculates and inserts any parity bits into outgoing frames and verifies the re ceived parity bits in incoming frames This is true for both asynchronous and synchronous modes even though it is mostly used in asynchronous communication The possible parity modes are defined in Table 16 5 USART Parity Bits on page 452 When even parity is chosen a ...

Page 454: ... cycle Given a desired baud rate brdesired the clock divider USARTn_CLKDIV can be calculated by using Figure 16 4 USART Desired Baud Rate on page 453 USARTn_CLKDIV 256 x fHFPERCLK oversample x brdesired 1 Figure 16 4 USART Desired Baud Rate Table 16 7 USART Baud Rates 4MHz Peripheral Clock with 20 bit CLKDIV on page 453 shows a set of desired baud rates and how accurately the USART is able to gene...

Page 455: ...mit buffer using one of the methods described in 16 3 2 6 Trans mit Buffer Operation When the transmission shift register is empty and ready for new data a frame from the transmit buffer is loaded into the shift register and if the transmitter is enabled transmission begins When the frame has been transmitted a new frame is loa ded into the shift register if available and transmission continues If...

Page 456: ...tion When writing more frames to the transmit buffer than there is free space for the TXOF interrupt flag in USARTn_IF will be set indicat ing the overflow The data already in the transmit buffer is preserved in this case and no data is written In addition to the interrupt flag TXC in USARTn_IF and status flag TXC in USARTn_STATUS which are set when the transmission is complete TXBL in USARTn_STAT...

Page 457: ...TRI If AUTOTRI is set TXTRI is always read as 0 Note When in SmartCard mode with repeat enabled none of the actions except generate break will be performed until the frame is trans mitted without failure Generation of a break in SmartCard mode with repeat enabled will cause the USART to detect a NACK on every frame 16 3 2 8 Data Reception Data reception is enabled by setting RXEN in USARTn_CMD Whe...

Page 458: ...LEX pull two frames out of the buffer If an attempt is done to read more frames from the buffer than what is available the RXUF interrupt flag in USARTn_IF is set to signal the underflow and the data read from the buffer is undefined Frames can be read from the receive buffer without removing the data by using USARTn_RXDATAXP and USARTn_RXDOUBLEXP USARTn_RXDATAXP gives access the first frame in th...

Page 459: ...loaded into the receive buffer even when RXBLOCK is set This is when an ad dress frame is received when operating in multi processor mode See 16 3 2 20 Multi Processor Mode for more information Frames received containing framing or parity errors will not result in the FERR and PERR interrupt flags in USARTn_IF being set while RXBLOCK in USARTn_STATUS is set Hardware recognition is not applied to t...

Page 460: ...vote can be disabled by setting MVDIS in USARTn_CTRL If the value of the start bit is found to be high the reception of the frame is aborted filtering out false start bits possibly generated by noise on the input 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 Idle Start bit Bit 0 0 1 2 3 4 5 6 7 8 1 2 3 4 5 6 13 7 12 OVS 0 OVS 1 0 1 2 3 4 5 6 1 OVS 2 1 2 3 4 1 2 3 4 OVS 3 2 3 4...

Page 461: ...RTn_RXDATAXP USARTn_RXDOUBLEX or USARTn_RXDOUBLEXP registers If ERRSTX in USARTn_CTRL is set the transmitter is disabled on received parity and framing errors If ERRSRX in USARTn_CTRL is set the receiver is disabled on parity and framing errors 16 3 2 13 Framing Error and Break Detection A framing error is the result of an asynchronous frame where the stop bit was sampled to a value of 0 This can ...

Page 462: ...ain Whether or not the output is tristated at a given time can be read from TXTRI in USARTn_STATUS If TXTRI is set when transmitting data the data is shifted out of the shift register but is not put out on U S n_TX When operating a half duplex data bus it is common to have a bus master which first transmits a request to one of the bus slaves then receives a reply In this case the frame transmissio...

Page 463: ...AL2 for the TX sequencer USn_CS is immediately deasserted when the transmitter becomes disabled Figure 16 10 USART Half Duplex Communication with External Driver on page 462 shows an example configuration where USn_CS is used to automatically enable and disable an external driver USART RX TX µC CS Figure 16 10 USART Half Duplex Communication with External Driver The USn_CS output is active low by ...

Page 464: ...16 11 USART Transmission of Large Frames on page 463 is the first element written to the FIFO or the least significant byte when writing two bytes at a time using USARTn_TXDOUBLE Write CTRL Write CTRL Write CTRL TX buffer element 1 TX buffer element 0 Shift register Peripheral Bus 0 1 2 3 4 5 6 7 0 1 2 0 1 2 0 1 2 3 4 5 6 7 Figure 16 11 USART Transmission of Large Frames As shown in Figure 16 11 U...

Page 465: ...rst byte read from the buffer thus contains the 8 least significant bits Set BYTESWAP to reverse the order The status bits are loaded into both elements of the receive buffer The frame is not moved from the receive shift register before there are two free spaces in the receive buffer Status RX buffer element 0 RX buffer element 1 Shift register Peripheral Bus Status Status 0 1 2 3 4 5 6 7 0 1 2 0 ...

Page 466: ...y the slave with RX enabled receives the data When transmission is complete the slave blocks the receiver and waits for a new address frame Figure 16 14 USART Multi processor Mode Example When a slave has received an address frame and wants to receive the following data it must make sure the receiver is unblocked before the next frame has been completely received in order to prevent data loss BIT8...

Page 467: ... 16 USART ISO 7816 Data Frame With Error on page 466 It holds the line low for one bit period before it releases the line In this case the guard time is exten ded by one bit period before a new transmission can start resulting in a total of 3 stop bits S 0 1 2 3 4 5 6 7 P Stop Start or idle Stop or idle ISO 7816 Frame with error Stop NAK Figure 16 16 USART ISO 7816 Data Frame With Error On a parit...

Page 468: ...can be performed 16 3 3 1 Frame Format The frames used in synchronous mode need no start and stop bits since a single clock is available to all parts participating in the com munication Parity bits cannot be used in synchronous mode The USART supports frame lengths of 4 to 16 bits per frame Larger frames can be simulated by transmitting multiple smaller frames i e a 22 bit frame can be sent using ...

Page 469: ...ither set up or sampled When CLKPHA in USARTn_CTRL is cleared data is sampled on the leading clock edge and set up is done on the trailing edge If CLKPHA is set however data is set up on the leading clock edge and sampled on the trailing edge In addition to this the polarity of the clock signal can be changed by setting CLKPOL in USARTn_CTRL which also defines the idle state of the clock This resu...

Page 470: ...t has been trans mitted and there is no more data in the transmit buffer The time between when CS is asserted and the first bit is transmitted can be controlled using the USART Timer and with CSSETUP in USARTn_TIMING Any of the three comparators can be used to set this delay If new data is ready for transmission before CS is deas serted the data is sent without deasserting CS in between CSHOLD in ...

Page 471: ...a If 2 bytes are expected from the slave then transmit 2 bytes with the transmitter tristated and the slave uses the generated bus clock to transmit data to the master TXTRI can be set by setting the TXTRIEN command bit in USARTn_CMD Note When operating as SPI slave in half duplex mode TX has to be tristated not disabled during data reception if the slave is to transmit data in the current transfe...

Page 472: ...Standard I2S waveform reduced accuracy on page 471 The first figure shows a waveform transmitted with full accuracy The wordlength can be configured to 32 bit 16 bit or 8 bit using FORMAT in USARTn_I2SCTRL In the second figure I2S data is transmitted with reduced accuracy i e the data transmitted has less bits than what is possible in the bus format Note that the msb of a word transmitted in regul...

Page 473: ...channel Right channel Right channel LSB LSB Figure 16 24 USART Right justified I2S waveform In mono mode the word select signal pulses at the beginning of each word instead of toggling for each word Mono I2S waveform is shown in Figure 16 25 USART Mono I2S waveform on page 472 USn_CLK USn_CS word select USn_TX USn_RX MSB Left channel Right channel Right channel LSB MSB Figure 16 25 USART Mono I2S ...

Page 474: ...full and the RX shift register is full regardless of the state of DBGHALT or chip halt Additional incoming data is discarded When DBGHALT is set RTS deasserts on RX buffer full or when chip halt is high However a low pulse detected on chip halt will keep RTS asserted when no frame is being received At the start of frame reception RTS will deas sert if chip halt is high and DBGHALT is set This beha...

Page 475: ...r the DMA controller to read from the USART receive buffer can come from the following source Data available in the receive buffer Data available in the receive buffer and data is for the RIGHT I2S channel Only used in I2S mode A write request can come from one of the following sources Transmit buffer and shift register empty No data to send Transmit buffer has room for more data Transmit buffer h...

Page 476: ...or is still enabled the counter continues counting By default the counter will count up to 256 and stop unless a RESTARTEN is set in one of the USARTn_TIMECMPn registers By using RESTARTEN and an interval programmed into TCMPVAL an interval timer can be set up The TSTART field needs to be changed to DISABLE to stop the interval timer The timer stops running once all of the compa rators are disable...

Page 477: ...ck Diagram The following sections will go into more details on programming the various usage cases Table 16 10 USART Application Settings for USARTn_TIMING and USARTn_TIMECMPn Application TSTARTn TSTOPn TCMPVALn Other Response Timeout TSTART0 TXEOF TSTOP0 RXACT TCMPVAL0 0x08 TCMP0 in USARTn_IEN Receiver Timeout TSTART1 RXEOF TSTOP1 RXACT TCMPVAL1 0x08 TCMP1 in USARTn_IEN Large Receiver Timeout TST...

Page 478: ... 0x0C TXARX0EN in USARTn_TRIGCTRL TCMP0 in USARTn_IEN Table 16 10 USART Application Settings for USARTn_TIMING and USARTn_TIMECMPn on page 476 shows some examples of how the USART timer can be programmed for various applications The following sections will describe more details for each applications shown in the table 16 3 10 1 Response Timeout Response Timeout is when a UART master sends a frame ...

Page 479: ... the desired timeout is reached Once the RX start bit is detected comparator 1 will be disabled If TIMERRESTARTED in USARTn_STATUS is clear the TCMP1 interrupt is the first interrupt after RXEOF RX RX RECEIVER TIMEOUT T C M P n I N T Figure 16 28 USART RX Timeout 16 3 10 3 Break Detect LIN bus and half duplex UARTs can take advantage of the timer configured for break detection where RX is held low...

Page 480: ...plication Settings for USARTn_TIMING and USARTn_TIMECMPn on page 476 for details on setting up this example For this example in Figure 16 30 USART TXSEQ Timing on page 479 ICS is set to TCMP2 in USARTn_TIMING To keep CS asserted during the inter character space set AUTOCS in USARTn_CTRL There are a few small pre set timing values provided for TX sequence timing Using these preset timing values can...

Page 481: ...in USARTn_TRIGCTRL to start the timer TSTART0 in USARTn_TIMECMP0 is set to RXEOF which enables the transitter of the timer delay For this example TCMPVAL in USARTn_TIMECMP0 is set to 0x20 to create a 32 baud time delay between the end of the RX frame and the start of the TX frame The break detect is configured by setting TSTART1 to RXACT to detect the start bit and setting TSTOP1 to RXACTN to dete...

Page 482: ...he IrDA modula tor The width of the pulses generated by the IrDA modulator is set by configuring IRPW in USARTn_IRCTRL Four pulse widths are availa ble each defined relative to the configured bit period as listed in Table 16 11 USART IrDA Pulse Widths on page 481 Table 16 11 USART IrDA Pulse Widths IRPW Pulse width OVS 0 Pulse width OVS 1 Pulse width OVS 2 Pulse width OVS 3 00 1 16 1 8 1 6 1 4 01 ...

Page 483: ...SARTn_TXDOUBLEX W TX Buffer Double Data Extended Register 0x03C USARTn_TXDOUBLE W TX Buffer Double Data Register 0x040 USARTn_IF R Interrupt Flag Register 0x044 USARTn_IFS W1 Interrupt Flag Set Register 0x048 USARTn_IFC R W1 Interrupt Flag Clear Register 0x04C USARTn_IEN RW Interrupt Enable Register 0x050 USARTn_IRCTRL RW IrDA Control Register 0x058 USARTn_INPUT RW USART Input Register 0x05C USART...

Page 484: ...Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name SMSDELAY MVDIS AUTOTX BYTESWAP SSSEARLY ERRSTX ERRSRX ERRSDMA BIT8DV SKIPPERRF SCRETRANS SCMODE AUTOTRI AUTOCS CSINV TXINV RXINV TXBIL CSMA MSBF CLKPHA CLKPOL OVS MPAB MPM CCEN LOOPBK SYNC EFM32JG1 Reference Manual USART Universal Synchronous Asynchronous Receiver Transmitter silabs com Smart Connected ...

Page 485: ...ynchronous mode only in the receiver Value Description 0 Received framing and parity errors have no effect on transmitter 1 Received framing and parity errors disable the transmitter 23 ERRSRX 0 RW Disable RX On Error When set the receiver is disabled on framing and parity errors asynchronous mode only Value Description 0 Framing and parity errors have no effect on receiver 1 Framing and parity er...

Page 486: ...ault value is active low This affects both the selection of external slaves as well as the selection of the microcontroller as a slave Value Description 0 Chip select is active low 1 Chip select is active high 14 TXINV 0 RW Transmitter output Invert The output from the USART transmitter can optionally be inverted by setting this bit Value Description 0 Output from the transmitter is passed unchang...

Page 487: ... bus clock in synchronous mode 1 SAMPLETRAILING Data is set up on the leading edge and sampled on the trailing edge of the bus clock in synchronous mode 8 CLKPOL 0 RW Clock Polarity Determines the clock polarity of the bus clock used in synchronous mode Value Mode Description 0 IDLELOW The bus clock used in synchronous mode has a low base value 1 IDLEHIGH The bus clock used in synchronous mode has...

Page 488: ...on checking on data when operating in half duplex modus Value Description 0 Collision check is disabled 1 Collision check is enabled The receiver must be enabled for the check to be performed 1 LOOPBK 0 RW Loopback Enable Allows the receiver to be connected directly to the USART transmitter for loopback and half duplex communication Value Description 0 The receiver is connected to and receives dat...

Page 489: ... 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x1 0x0 0x5 Access RW RW RW Name STOPBITS PARITY DATABITS EFM32JG1 Reference Manual USART Universal Synchronous Asynchronous Receiver Transmitter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 488 ...

Page 490: ...E Parity bits are not used 2 EVEN Even parity are used Parity bits are automatically generated and checked by hardware 3 ODD Odd parity is used Parity bits are automatically generated and checked by hardware 7 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 3 0 DATABITS 0x5 RW Data Bit Mode This register sets the number of data bit...

Page 491: ...Access Description 13 SIXTEEN Each frame contains 16 data bits EFM32JG1 Reference Manual USART Universal Synchronous Asynchronous Receiver Transmitter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 490 ...

Page 492: ...3 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 0 0 0 0 0 0 0 0 0 Access RW RW RW RW RW RW RW RW RW RW Name TSEL RXATX2EN RXATX1EN RXATX0EN TXARX2EN TXARX1EN TXARX0EN AUTOTXTEN TXTEN RXTEN EFM32JG1 Reference Manual USART Universal Synchronous Asynchronous Receiver Transmitter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 491 ...

Page 493: ... plus TCMPVAL1 baud times When set a TX end of frame will trigger the receiver after a TCMPVAL1 baud time delay 10 RXATX0EN 0 RW Enable Receive Trigger after TX end of frame plus TCMPVAL0 baud times When set a TX end of frame will trigger the receiver after a TCMPVAL0 baud time delay 9 TXARX2EN 0 RW Enable Transmit Trigger after RX End of Frame plus TCMP2VAL When set an RX end of frame will trigge...

Page 494: ...N enabling the receiver on positive trigger edges 3 0 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions EFM32JG1 Reference Manual USART Universal Synchronous Asynchronous Receiver Transmitter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 493 ...

Page 495: ...CK resulting in all incoming frames being loaded into the receive buffer 6 RXBLOCKEN 0 W1 Receiver Block Enable Set to set RXBLOCK resulting in all incoming frames being discarded 5 MASTERDIS 0 W1 Master Disable Set to disable master mode clearing the MASTER status bit and putting the USART in slave mode 4 MASTEREN 0 W1 Master Enable Set to enable master mode setting the MASTER status bit Master m...

Page 496: ...x0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 Access R R R R R R R R R R R R R R R R Name TXBUFCNT TIMERRESTARTED TXIDLE RXFULLRIGHT RXDATAVRIGHT TXBSRIGHT TXBDRIGHT RXFULL RXDATAV TXBL TXC TXTRI RXBLOCK MASTER TXENS RXENS EFM32JG1 Reference Manual USART Universal Synchronous Asynchronous Receiver Transmitter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 495 ...

Page 497: ...Expects Double Right Data When set the TX buffer expects double right data Else it may expect a single right data or left data Only used in I2S mode 8 RXFULL 0 R RX FIFO Full Set when the RXFIFO is full Cleared when the receive buffer is no longer full When this bit is set there is still room for one more frame in the receive shift register 7 RXDATAV 0 R RX Data Valid Set when data is available in...

Page 498: ... rate based on receiving a 0x55 frame 0x00 for IrDA This is used in Asynchronous mode 30 23 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 22 3 DIV 0x00000 RWH Fractional Clock Divider Specifies the fractional clock divider for the USART Setting AUTOBAUDEN in USARTn_CLKDIV will overwrite the DIV field 2 0 Reserved To ensure compatib...

Page 499: ...evices always write bits to 0 More information in 1 2 Conven tions 8 0 RXDATA 0x000 R RX Data Use this register to access data read from the USART Buffer is cleared on read access 16 5 8 USARTn_RXDATA RX Buffer Data Register Actionable Reads Offset Bit Position 0x01C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 Access R Name RXDATA Bit Name Reset...

Page 500: ...ly 29 25 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 24 16 RXDATA1 0x000 R RX Data 1 Second frame read from buffer 15 FERR0 0 R Data Framing Error 0 Set if data in buffer has a framing error Can be the result of a break condition 14 PERR0 0 R Data Parity Error 0 Set if data in buffer has a parity error asynchronous mode only 13 9...

Page 501: ...18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0x000 Access R R R Name FERRP PERRP RXDATAP Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 15 FERRP 0 R Data Framing Error Peek Set if data in buffer has a framing error Can be the result of a break condition 14 PERRP 0 R Data Parity Err...

Page 502: ...25 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 24 16 RXDATAP1 0x000 R RX Data 1 Peek Second frame read from FIFO 15 FERRP0 0 R Data Framing Error 0 Peek Set if data in buffer has a framing error Can be the result of a break condition 14 PERRP0 0 R Data Parity Error 0 Peek Set if data in buffer has a parity error asynchronous mode...

Page 503: ...ission 13 TXBREAK 0 W Transmit Data As Break Set to send data as a break Recipient will see a framing error or a break condition depending on its configuration and the value of TXDATA 12 TXTRIAT 0 W Set TXTRI After Transmission Set to tristate transmitter by setting TXTRI after transmission 11 UBRXAT 0 W Unblock RX After Transmission Set to clear RXBLOCK after transmission unblocking the receiver ...

Page 504: ... 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 7 0 TXDATA 0x00 W TX Data This frame will be added to TX buffer Only 8 LSB can be written using this register 9th bit and control bits will be cleared EFM32JG1 Reference Manual USART Universal Synchronous Asynchronous Receiver Transmitter silabs com Smart Connected Energy friendly...

Page 505: ...after transmission unblocking the receiver 26 25 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 24 16 TXDATA1 0x000 W TX Data Second frame to write to FIFO 15 RXENAT0 0 W Enable RX After Transmission Set to enable reception after transmission 14 TXDISAT0 0 W Clear TXEN After Transmission Set to disable transmitter and release data b...

Page 506: ...Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 15 8 TXDATA1 0x00 W TX Data Second frame to write to buffer 7 0 TXDATA0 0x00 W TX Data First frame to write to buffer EFM32JG1 Reference Manual USART Universal Synchronous Asynchronous Receiver Transmitter silabs com Smart Connected Energy friendly Pr...

Page 507: ...5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Access R R R R R R R R R R R R R R R R R Name TCMP2 TCMP1 TCMP0 TXIDLE CCF SSM MPAF FERR PERR TXUF TXOF RXUF RXOF RXFULL RXDATAV TXBL TXC EFM32JG1 Reference Manual USART Universal Synchronous Asynchronous Receiver Transmitter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 506 ...

Page 508: ...nchronous mode only is received while RXBLOCK is cleared 7 TXUF 0 R TX Underflow Interrupt Flag Set when operating as a synchronous slave no data is available in the transmit buffer when the master starts transmission of a new frame 6 TXOF 0 R TX Overflow Interrupt Flag Set when a write is done to the transmit buffer while it is full The data already in the transmit buffer is preserved 5 RXUF 0 R ...

Page 509: ... 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 Name TCMP2 TCMP1 TCMP0 TXIDLE CCF SSM MPAF FERR PERR TXUF TXOF RXUF RXOF RXFULL TXC EFM32JG1 Reference Manual USART Universal Synchronous Asynchronous Receiver Transmitter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 508 ...

Page 510: ...rrupt flag 9 FERR 0 W1 Set FERR Interrupt Flag Write 1 to set the FERR interrupt flag 8 PERR 0 W1 Set PERR Interrupt Flag Write 1 to set the PERR interrupt flag 7 TXUF 0 W1 Set TXUF Interrupt Flag Write 1 to set the TXUF interrupt flag 6 TXOF 0 W1 Set TXOF Interrupt Flag Write 1 to set the TXOF interrupt flag 5 RXUF 0 W1 Set RXUF Interrupt Flag Write 1 to set the RXUF interrupt flag 4 RXOF 0 W1 Se...

Page 511: ... 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access R W1 R W1 R W1 R W1 R W1 R W1 R W1 R W1 R W1 R W1 R W1 R W1 R W1 R W1 R W1 Name TCMP2 TCMP1 TCMP0 TXIDLE CCF SSM MPAF FERR PERR TXUF TXOF RXUF RXOF RXFULL TXC EFM32JG1 Reference Manual USART Universal Synchronous Asynchronous Receiver Transmitter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 510 ...

Page 512: ...alue of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 9 FERR 0 R W1 Clear FERR Interrupt Flag Write 1 to clear the FERR interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 8 PERR 0 R W1 Clear PERR Interrupt Flag Write 1 to clear the PERR interrupt flag Reading...

Page 513: ...XC 0 R W1 Clear TXC Interrupt Flag Write 1 to clear the TXC interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC EFM32JG1 Reference Manual USART Universal Synchronous Asynchronous Receiver Transmitter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 512 ...

Page 514: ... 1 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name TCMP2 TCMP1 TCMP0 TXIDLE CCF SSM MPAF FERR PERR TXUF TXOF RXUF RXOF RXFULL RXDATAV TXBL TXC EFM32JG1 Reference Manual USART Universal Synchronous Asynchronous Receiver Transmitter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 513 ...

Page 515: ...9 FERR 0 RW FERR Interrupt Enable Enable disable the FERR interrupt 8 PERR 0 RW PERR Interrupt Enable Enable disable the PERR interrupt 7 TXUF 0 RW TXUF Interrupt Enable Enable disable the TXUF interrupt 6 TXOF 0 RW TXOF Interrupt Enable Enable disable the TXOF interrupt 5 RXUF 0 RW RXUF Interrupt Enable Enable disable the RXUF interrupt 4 RXOF 0 RW RXOF Interrupt Enable Enable disable the RXOF in...

Page 516: ...3 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 0 0 0x0 0 Access RW RW RW RW RW Name IRPRSSEL IRPRSEN IRFILT IRPW IREN EFM32JG1 Reference Manual USART Universal Synchronous Asynchronous Receiver Transmitter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 515 ...

Page 517: ... input to IrDA module instead of TX 6 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 3 IRFILT 0 RW IrDA RX Filter Set to enable filter on IrDA demodulator Value Description 0 No filter enabled 1 Filter enabled IrDA pulse must be high for at least 4 consecutive clock cycles to be detected 2 1 IRPW 0x0 RW IrDA TX Pulse Width Configu...

Page 518: ...4 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0x0 0 0x0 Access RW RW RW RW Name CLKPRS CLKPRSSEL RXPRS RXPRSSEL EFM32JG1 Reference Manual USART Universal Synchronous Asynchronous Receiver Transmitter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 517 ...

Page 519: ...ected 8 PRSCH8 PRS Channel 8 selected 9 PRSCH9 PRS Channel 9 selected 10 PRSCH10 PRS Channel 10 selected 11 PRSCH11 PRS Channel 11 selected 7 RXPRS 0 RW PRS RX Enable When set the PRS channel selected as input to RX 6 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 3 0 RXPRSSEL 0x0 RW RX PRS Channel Select Select PRS channel as inp...

Page 520: ...ption 10 PRSCH10 PRS Channel 10 selected 11 PRSCH11 PRS Channel 11 selected EFM32JG1 Reference Manual USART Universal Synchronous Asynchronous Receiver Transmitter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 519 ...

Page 521: ...bit data 7 W8D8 8 bit word 8 bit data 7 5 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 4 DELAY 0 RW Delay on I2S data Set to add a one cycle delay between a transition on the word clock and the start of the I2S word Should be set for stand ard I2S format 3 DMASPLIT 0 RW Separate DMA Request For Left Right Data When set DMA request...

Page 522: ...23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 0x0 0x0 0x0 Access RW RW RW RW Name CSHOLD ICS CSSETUP TXDELAY EFM32JG1 Reference Manual USART Universal Synchronous Asynchronous Receiver Transmitter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 521 ...

Page 523: ...n using USART_TIMECMPn normally set TSTART to DISABLE to stop general timer and to prevent unwanted interrupts Value Mode Description 0 ZERO There is no space between charcters 1 ONE Create a space of 1 baud times before start of transmission 2 TWO Create a space of 2 baud times before start of transmission 3 THREE Create a space of 3 baud times before start of transmission 4 SEVEN Create a space ...

Page 524: ...lly set TSTART to DISABLE to stop general timer and to prevent unwanted interrupts Value Mode Description 0 DISABLE Disable TXDELAY in USARTn_CTRL can be used for legacy 1 ONE Start of transmission is delayed for 1 baud times 2 TWO Start of transmission is delayed for 2 baud times 3 THREE Start of transmission is delayed for 3 baud times 4 SEVEN Start of transmission is delayed for 7 baud times 5 ...

Page 525: ...ll contin ue transmitting the next TXBUFn data will not load into the TX shift register Value Description 0 Ingore CTS 1 Stop transmitting when CTS is negated 1 CTSINV 0 RW CTS Pin Inversion When set the CTS pin polarity is inverted Value Description 0 The USn_CTS pin is low true 1 The USn_CTS pin is high true 0 DBGHALT 0 RW Debug halt Value Description 0 Continue to transmit until TX buffer is em...

Page 526: ...28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0x0 0x0 0x00 Access RW RW RW RW Name RESTARTEN TSTOP TSTART TCMPVAL EFM32JG1 Reference Manual USART Universal Synchronous Asynchronous Receiver Transmitter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 525 ...

Page 527: ...led on RX going Inactive 19 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 18 16 TSTART 0x0 RW Timer start source Source used to start comparator 0 and timer Value Mode Description 0 DISABLE Comparator 0 is disabled 1 TXEOF Comparator 0 and timer are started at TX end of frame 2 TXC Comparator 0 and timer are started at TX Complete ...

Page 528: ...28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0x0 0x0 0x00 Access RW RW RW RW Name RESTARTEN TSTOP TSTART TCMPVAL EFM32JG1 Reference Manual USART Universal Synchronous Asynchronous Receiver Transmitter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 527 ...

Page 529: ... RX going Inactive 19 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 18 16 TSTART 0x0 RW Timer start source Source used to start comparator 1 and timer Value Mode Description 0 DISABLE Comparator 1 is disabled 1 TXEOF Comparator 1 and timer are started at TX end of frame 2 TXC Comparator 1 and timer are started at TX Complete 3 RXAC...

Page 530: ...28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0x0 0x0 0x00 Access RW RW RW RW Name RESTARTEN TSTOP TSTART TCMPVAL EFM32JG1 Reference Manual USART Universal Synchronous Asynchronous Receiver Transmitter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 529 ...

Page 531: ... RX going Inactive 19 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 18 16 TSTART 0x0 RW Timer start source Source used to start comparator 2 and timer Value Mode Description 0 DISABLE Comparator 2 is disabled 1 TXEOF Comparator 2 and timer are started at TX end of frame 2 TXC Comparator 2 and timer are started at TX Complete 3 RXAC...

Page 532: ...4 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 Access RW RW RW RW RW RW Name RTSPEN CTSPEN CLKPEN CSPEN TXPEN RXPEN EFM32JG1 Reference Manual USART Universal Synchronous Asynchronous Receiver Transmitter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 531 ...

Page 533: ...is enabled Value Description 0 The USn_CLK pin is disabled 1 The USn_CLK pin is enabled 2 CSPEN 0 RW CS Pin Enable When set the CS pin of the USART is enabled Value Description 0 The USn_CS pin is disabled 1 The USn_CS pin is enabled 1 TXPEN 0 RW TX Pin Enable When set the TX MOSI pin of the USART is enabled Value Description 0 The U S n_TX MOSI pin is disabled 1 The U S n_TX MOSI pin is enabled 0...

Page 534: ...6 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 0x00 0x00 0x00 Access RW RW RW RW Name CLKLOC CSLOC TXLOC RXLOC EFM32JG1 Reference Manual USART Universal Synchronous Asynchronous Receiver Transmitter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 533 ...

Page 535: ...cation 9 10 LOC10 Location 10 11 LOC11 Location 11 12 LOC12 Location 12 13 LOC13 Location 13 14 LOC14 Location 14 15 LOC15 Location 15 16 LOC16 Location 16 17 LOC17 Location 17 18 LOC18 Location 18 19 LOC19 Location 19 20 LOC20 Location 20 21 LOC21 Location 21 22 LOC22 Location 22 23 LOC23 Location 23 24 LOC24 Location 24 25 LOC25 Location 25 26 LOC26 Location 26 27 LOC27 Location 27 28 LOC28 Loca...

Page 536: ...ation 9 10 LOC10 Location 10 11 LOC11 Location 11 12 LOC12 Location 12 13 LOC13 Location 13 14 LOC14 Location 14 15 LOC15 Location 15 16 LOC16 Location 16 17 LOC17 Location 17 18 LOC18 Location 18 19 LOC19 Location 19 20 LOC20 Location 20 21 LOC21 Location 21 22 LOC22 Location 22 23 LOC23 Location 23 24 LOC24 Location 24 25 LOC25 Location 25 26 LOC26 Location 26 27 LOC27 Location 27 28 LOC28 Locat...

Page 537: ...tion 9 10 LOC10 Location 10 11 LOC11 Location 11 12 LOC12 Location 12 13 LOC13 Location 13 14 LOC14 Location 14 15 LOC15 Location 15 16 LOC16 Location 16 17 LOC17 Location 17 18 LOC18 Location 18 19 LOC19 Location 19 20 LOC20 Location 20 21 LOC21 Location 21 22 LOC22 Location 22 23 LOC23 Location 23 24 LOC24 Location 24 25 LOC25 Location 25 26 LOC26 Location 26 27 LOC27 Location 27 28 LOC28 Locati...

Page 538: ...ion 9 10 LOC10 Location 10 11 LOC11 Location 11 12 LOC12 Location 12 13 LOC13 Location 13 14 LOC14 Location 14 15 LOC15 Location 15 16 LOC16 Location 16 17 LOC17 Location 17 18 LOC18 Location 18 19 LOC19 Location 19 20 LOC20 Location 20 21 LOC21 Location 21 22 LOC22 Location 22 23 LOC23 Location 23 24 LOC24 Location 24 25 LOC25 Location 25 26 LOC26 Location 26 27 LOC27 Location 27 28 LOC28 Locatio...

Page 539: ...30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 0x00 Access RW RW Name RTSLOC CTSLOC EFM32JG1 Reference Manual USART Universal Synchronous Asynchronous Receiver Transmitter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 538 ...

Page 540: ...ation 9 10 LOC10 Location 10 11 LOC11 Location 11 12 LOC12 Location 12 13 LOC13 Location 13 14 LOC14 Location 14 15 LOC15 Location 15 16 LOC16 Location 16 17 LOC17 Location 17 18 LOC18 Location 18 19 LOC19 Location 19 20 LOC20 Location 20 21 LOC21 Location 21 22 LOC22 Location 22 23 LOC23 Location 23 24 LOC24 Location 24 25 LOC25 Location 25 26 LOC26 Location 26 27 LOC27 Location 27 28 LOC28 Locat...

Page 541: ...tion 9 10 LOC10 Location 10 11 LOC11 Location 11 12 LOC12 Location 12 13 LOC13 Location 13 14 LOC14 Location 14 15 LOC15 Location 15 16 LOC16 Location 16 17 LOC17 Location 17 18 LOC18 Location 18 19 LOC19 Location 19 20 LOC20 Location 20 21 LOC21 Location 21 22 LOC22 Location 22 23 LOC23 Location 23 24 LOC24 Location 24 25 LOC25 Location 25 26 LOC26 Location 26 27 LOC27 Location 27 28 LOC28 Locati...

Page 542: ... EFM is in low energy mode EM2 DeepSleep with most core functionality turned off the LEUART can wait for an in coming UART frame while having an extremely low energy consumption When a UART frame is completely received the CPU can quickly be woken up Alternatively multiple frames can be transferred via the Direct Memory Access DMA module into RAM memory before waking up the CPU Received data can o...

Page 543: ... parity bit generation and check Configurable number of stop bits 1 or 2 Capable of sleep mode wake up on received frame Either wake up on any received byte or Wake up only on specified start and signal frames Supports transmission and reception in EM0 Active EM1 Sleep and EM2 DeepSleep with Full DMA support Specified start frame can start reception automatically IrDA modulator pulse generator pul...

Page 544: ...EUn_RX UART Control and status Peripheral Bus TX Baud rate generator RX Baud rate generator Start frame STARTFRAME RX Wakeup SYNC Pulse extend Pulse gen Signal frame SIGFRAME Start frame interrupt RXBLOCK LEUn_TX Figure 17 1 LEUART Overview EFM32JG1 Reference Manual LEUART Low Energy Universal Asynchronous Receiver Transmitter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 543 ...

Page 545: ...lting in a low idle state a high start bit inverted data and parity bits and low stop bits INV should only be changed while the receiver is disabled 17 3 1 1 Parity Bit Calculation and Handling Hardware automatically inserts parity bits into outgoing frames and checks the parity bits of incoming frames The possible parity modes are defined in Table 17 1 LEUART Parity Bit on page 544 When even pari...

Page 546: ...ud rates and the closest baud rates reachable by the LEUART with a 32 768 kHz clock source It also shows the average baud rate error Table 17 2 LEUART Baud Rates Desired baud rate LEUARTn_CLKDIV LEUARTn_CLKDIV 256 Actual baud rate Error 300 27704 108 21875 300 0217 0 01 600 13728 53 625 599 8719 0 02 1200 6736 26 3125 1199 744 0 02 2400 3240 12 65625 2399 487 0 02 4800 1488 5 8125 4809 982 0 21 96...

Page 547: ...mission of this frame will be completed An overview of the operation of the transmitter is shown in Figure 17 5 LEUART Transmitter Overview on page 546 LEUn_TX Transmit shift register TXENS d0 d8 control d0 d2 d4 d6 d8 d7 d5 d3 d1 control TXDATA TXDATAX BIT8DV Transmit buffer 0 Figure 17 5 LEUART Transmitter Overview 17 3 4 2 Frame Transmission Control The transmission control bits which can be wr...

Page 548: ...RXDATAV interrupt flag in LEUARTn_IF are set Both the RXDATAV status flag and the RXDATAV interrupt flag are cleared by hardware when data is no longer available i e when data has been read out of the buffer Data can be read from receive buffer using either LEUARTn_RXDATA or LEUARTn_RXDATAX LEUARTn_RXDATA gives access to the 8 least significant bits of the received frame while LEUARTn_RXDATAX must...

Page 549: ...t time The overflow interrupt flag RXOF in LEUARTn_IF will be set if a frame in the receive shift register waiting to be loaded into the receive buffer is overwritten by an incoming frame even though RXBLOCK is set 17 3 5 3 Data Sampling The receiver samples each incoming bit as close as possible to the middle of the bit period Except for the start bit only a single sam ple is taken of each of the...

Page 550: ... STARTF interrupt flag in LEUARTn_IF being set regardless of the value of SFUBRX in LEUARTn_CTRL This allows an interrupt to be made when the start frame is detected When 8 data bit frame formats are used only the 8 least significant bits of LEUARTn_STARTFRAME are compared to incoming frames The full length of LEUARTn_STARTFRAME is used when operating with frames consisting of 9 data bits Note The...

Page 551: ...coming frame An address frame with a parity error or a framing error is not detected as an address frame The Start Signal and address frames should not be set to match the same frame since each of these uses separate synchronization to the peripherial clock domain 17 3 6 Loopback The LEUART receiver samples LEUn_RX by default and the transmitter drives LEUn_TX by default This is not the only confi...

Page 552: ...iver must be controlled by a GPIO Figure 17 10 LEUART Half Duplex Communication with External Driver on page 551 shows an example configuration using an external driv er LEUART RX TX µC GPIO Figure 17 10 LEUART Half Duplex Communication with External Driver 17 3 7 3 Two Data links Some limited devices only support half duplex communication even though two data links are available In this case soft...

Page 553: ... buffer empty In some cases it may be sensible to temporarily stop DMA access to the LEUART when a parity or framing error has occurred This is enabled by setting ERRSDMA in LEUARTn_CTRL When this bit is set the DMA controller will not get requests from the receive buffer if a framing error or parity error is detected in the received byte The ERRSDMA bit applies only to the RX DMA When operating i...

Page 554: ...horter than half a UART bit period At 2400 baud or lower the pulse generator is able to generate RZI pulses compatible with the IrDA physical layer specification The external IrDA device must generate pulses of sufficient length for successful two way communication PULSEFILT in the LEUARTn_PULSECTRL register can be used to extend the minimum receive pulse width from 2 clock periods to 3 clock peri...

Page 555: ...x024 LEUARTn_TXDATAX W Transmit Buffer Data Extended Register 0x028 LEUARTn_TXDATA W Transmit Buffer Data Register 0x02C LEUARTn_IF R Interrupt Flag Register 0x030 LEUARTn_IFS W1 Interrupt Flag Set Register 0x034 LEUARTn_IFC R W1 Interrupt Flag Clear Register 0x038 LEUARTn_IEN RW Interrupt Enable Register 0x03C LEUARTn_PULSECTRL RW Pulse Control Register 0x040 LEUARTn_FREEZE RW Freeze Register 0x0...

Page 556: ... 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 0 0 0 0 0 0 0 0 0 0 0x0 0 0 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name TXDELAY TXDMAWU RXDMAWU BIT8DV MPAB MPM SFUBRX LOOPBK ERRSDMA INV STOPBITS PARITY DATABITS AUTOTRI EFM32JG1 Reference Manual LEUART Low Energy Universal Asynchronous Receiver Transmitter silabs com Smart Connected Energy friendly Pre...

Page 557: ...s about data being available in the receive buffer 1 DMA is available in EM2 for the request about data in the receive buffer 11 BIT8DV 0 RW Bit 8 Default Value When 9 bit frames are transmitted the default value of the 9th bit is given by BIT8DV If TXDATA is used to write a frame then the value of BIT8DV is assigned to the 9th bit of the outgoing frame If a frame is written with TXDATAX however t...

Page 558: ...X Value Description 0 A high value on the input output is 1 and a low value is 0 1 A low value on the input output is 1 and a high value is 0 4 STOPBITS 0 RW Stop Bit Mode Determines the number of stop bits used Only used when transmitting data The receiver only verifies that one stop bit is present Value Mode Description 0 ONE One stop bit is transmitted with every frame 1 TWO Two stop bits are t...

Page 559: ... When set LEUn_TX is tristated whenever the transmitter is inactive Value Description 0 LEUn_TX is held high when the transmitter is inactive INV inverts the inactive state 1 LEUn_TX is tristated when the transmitter is inactive EFM32JG1 Reference Manual LEUART Low Energy Universal Asynchronous Receiver Transmitter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 558 ...

Page 560: ...CLEARTX 0 W1 Clear TX Set to clear transmit buffer and the TX shift register 5 RXBLOCKDIS 0 W1 Receiver Block Disable Set to clear RXBLOCK resulting in all incoming frames being loaded into the receive buffer 4 RXBLOCKEN 0 W1 Receiver Block Enable Set to set RXBLOCK resulting in all incoming frames being discarded 3 TXDIS 0 W1 Transmitter Disable Set to disable transmission 2 TXEN 0 W1 Transmitter...

Page 561: ...hen the transmit buffer is empty and cleared when it is full 3 TXC 0 R TX Complete Set when a transmission has completed and no more data is available in the transmit buffer Cleared when a new transmis sion starts 2 RXBLOCK 0 R Block Incoming Data When set the receiver discards incoming frames An incoming frame will not be loaded into the receive buffer if this bit is set at the instant the frame ...

Page 562: ...lways be 0 2 0 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 17 5 5 LEUARTn_STARTFRAME Start Frame Register Async Reg For More information about Registers please see 4 3 Access to Low Energy Peripherals Asynchronous Registers Offset Bit Position 0x010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2...

Page 563: ...n 0x018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0x000 Access R R R Name FERR PERR RXDATA Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 15 FERR 0 R Receive Data Framing Error Set if data in buffer has a framing error Can be the result of ...

Page 564: ...23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0x000 Access R R R Name FERRP PERRP RXDATAP Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 15 FERRP 0 R Receive Data Framing Error Peek Set if data in buffer has a framing error Can be the result of a break condition 14 PE...

Page 565: ...ansmission has competed Value Description 0 The transmitter is not disabled after the frame has been transmitted 1 The transmitter is disabled clearing TXENS after the frame has been transmitted 13 TXBREAK 0 W Transmit Data As Break Set to send data as a break Recipient will see a framing error or a break condition depending on its configuration and the value of TXDATA Value Description 0 The spec...

Page 566: ...x00 Access W Name TXDATA Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 7 0 TXDATA 0x00 W TX Data This frame will be added to the transmit buffer Only 8 LSB can be written using this register 9th bit and control bits will be cleared EFM32JG1 Reference Manual LEUART Low Energy Universal Asynchro...

Page 567: ...se different synchronizers 7 FERR 0 R Framing Error Interrupt Flag Set when a frame with a framing error is received while RXBLOCK is cleared 6 PERR 0 R Parity Error Interrupt Flag Set when a frame with a parity error is received while RXBLOCK is cleared 5 TXOF 0 R TX Overflow Interrupt Flag Set when a write is done to the transmit buffer while it is full The data already in the transmit buffer is...

Page 568: ... 0 W1 Set MPAF Interrupt Flag Write 1 to set the MPAF interrupt flag 7 FERR 0 W1 Set FERR Interrupt Flag Write 1 to set the FERR interrupt flag 6 PERR 0 W1 Set PERR Interrupt Flag Write 1 to set the PERR interrupt flag 5 TXOF 0 W1 Set TXOF Interrupt Flag Write 1 to set the TXOF interrupt flag 4 RXUF 0 W1 Set RXUF Interrupt Flag Write 1 to set the RXUF interrupt flag 3 RXOF 0 W1 Set RXOF Interrupt ...

Page 569: ...d clears the corresponding interrupt flags This feature must be enabled globally in MSC 6 PERR 0 R W1 Clear PERR Interrupt Flag Write 1 to clear the PERR interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 5 TXOF 0 R W1 Clear TXOF Interrupt Flag Write 1 to clear the TXOF interrupt flag Reading returns the valu...

Page 570: ...terrupt 8 MPAF 0 RW MPAF Interrupt Enable Enable disable the MPAF interrupt 7 FERR 0 RW FERR Interrupt Enable Enable disable the FERR interrupt 6 PERR 0 RW PERR Interrupt Enable Enable disable the PERR interrupt 5 TXOF 0 RW TXOF Interrupt Enable Enable disable the TXOF interrupt 4 RXUF 0 RW RXUF Interrupt Enable Enable disable the RXUF interrupt 3 RXOF 0 RW RXOF Interrupt Enable Enable disable the...

Page 571: ...n tions 5 PULSEFILT 0 RW Pulse Filter Enable a one cycle pulse filter for pulse extender Value Description 0 Filter is disabled Pulses must be at least 2 cycles long for reliable de tection 1 Filter is enabled Pulses must be at least 3 cycles long for reliable de tection 4 PULSEEN 0 RW Pulse Generator Extender Enable Filter LEUART output through pulse generator and the LEUART input through the pul...

Page 572: ... REGFREEZE 0 RW Register Update Freeze When set the update of the LEUART logic from registers is postponed until this bit is cleared Use this bit to update several registers simultaneously Value Mode Description 0 UPDATE Each write access to a LEUART register is updated into the Low Fre quency domain as soon as possible 1 FREEZE The LEUART is not updated with the new written value EFM32JG1 Referen...

Page 573: ...hen the value written to TXDATA is being synchronized 5 TXDATAX 0 R TXDATAX Register Busy Set when the value written to TXDATAX is being synchronized 4 SIGFRAME 0 R SIGFRAME Register Busy Set when the value written to SIGFRAME is being synchronized 3 STARTFRAME 0 R STARTFRAME Register Busy Set when the value written to STARTFRAME is being synchronized 2 CLKDIV 0 R CLKDIV Register Busy Set when the...

Page 574: ...s write bits to 0 More information in 1 2 Conven tions 1 TXPEN 0 RW TX Pin Enable When set the TX pin of the LEUART is enabled Value Description 0 The LEUn_TX pin is disabled 1 The LEUn_TX pin is enabled 0 RXPEN 0 RW RX Pin Enable When set the RX pin of the LEUART is enabled Value Description 0 The LEUn_RX pin is disabled 1 The LEUn_RX pin is enabled EFM32JG1 Reference Manual LEUART Low Energy Uni...

Page 575: ...1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 0x00 Access RW RW Name TXLOC RXLOC EFM32JG1 Reference Manual LEUART Low Energy Universal Asynchronous Receiver Transmitter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 574 ...

Page 576: ...ocation 7 8 LOC8 Location 8 9 LOC9 Location 9 10 LOC10 Location 10 11 LOC11 Location 11 12 LOC12 Location 12 13 LOC13 Location 13 14 LOC14 Location 14 15 LOC15 Location 15 16 LOC16 Location 16 17 LOC17 Location 17 18 LOC18 Location 18 19 LOC19 Location 19 20 LOC20 Location 20 21 LOC21 Location 21 22 LOC22 Location 22 23 LOC23 Location 23 24 LOC24 Location 24 25 LOC25 Location 25 26 LOC26 Location ...

Page 577: ...ation 7 8 LOC8 Location 8 9 LOC9 Location 9 10 LOC10 Location 10 11 LOC11 Location 11 12 LOC12 Location 12 13 LOC13 Location 13 14 LOC14 Location 14 15 LOC15 Location 15 16 LOC16 Location 16 17 LOC17 Location 17 18 LOC18 Location 18 19 LOC19 Location 19 20 LOC20 Location 20 21 LOC21 Location 21 22 LOC22 Location 22 23 LOC23 Location 23 24 LOC24 Location 24 25 LOC25 Location 25 26 LOC26 Location 26...

Page 578: ...ite bits to 0 More information in 1 2 Conven tions 3 0 RXPRSSEL 0x0 RW RX PRS Channel Select Select PRS channel as input to RX Value Mode Description 0 PRSCH0 PRS Channel 0 selected 1 PRSCH1 PRS Channel 1 selected 2 PRSCH2 PRS Channel 2 selected 3 PRSCH3 PRS Channel 3 selected 4 PRSCH4 PRS Channel 4 selected 5 PRSCH5 PRS Channel 5 selected 6 PRSCH6 PRS Channel 6 selected 7 PRSCH7 PRS Channel 7 sel...

Page 579: ...exible 16 bit timer can be configured to provide PWM waveforms with optional dead time insertion e g motor control or work as a frequency genera tor The timer can also count events and control oth er peripherals through the PRS which offloads the CPU and reduces energy consumption 18 1 Introduction The 16 bit general purpose timer has 3 or 4 compare capture channels for input capture and compare P...

Page 580: ... Output Compare Compare output toggle pulse on compare match Immediate update of compare registers PWM Up count PWM Up down count PWM Predictable initial PWM output state configured by SW Buffered compare register to ensure glitch free update of compare values Clock sources HFPERCLKTIMERn 10 bit Prescaler External pin Peripheral Reflex System Debug mode Configurable to either run or stop when proc...

Page 581: ... 18 3 1 Counter Modes The timer consists of a counter that can be configured to the following modes 1 Up count Counter counts up until it reaches the value in TIMERn_TOP where it is reset to 0 before counting up again 2 Down count The counter starts at the value in TIMERn_TOP and counts down When it reaches 0 it is reloaded with the value in TIMERn_TOP 3 Up Down count The counter starts at 0 and c...

Page 582: ...h either an external pin or PRS input This is done through the input logic for the Com pare Capture Channel 0 The Timer Counter allows individual actions start stop reload to be taken for rising and falling input edges This is configured in the RISEA and FALLA fields in TIMERn_CTRL The reload value is 0 in up count and up down count mode and TOP in down count mode The RUNNING bit in TIMERn_STATUS ...

Page 583: ...r frequency than fHFPERCLK 3 when running from a pin input or a PRS input with FILT enabled in TIMERn_CCx_CTRL When running from PRS without FILT the frequency can be as high as fHFPERCLK Note that when clocking the timer from the same pulse that triggers a start through RISEA FALLA in TIMERn_CTRL the starting pulse will not update the Counter Value 18 3 1 6 Underflow Overflow from Neighboring Tim...

Page 584: ...t been written to the TIMERn_TOP register see Figure 18 5 TIMER TOP Value Update Functionality on page 583 Note When writing to TIMERn_TOP register directly the TIMERn_TOPB register value will be invalidated and the TOPBV flag will be cleared This prevents TIMERn_TOP register from being immmediately updated by an existing vaild TIMERn_TOPB value during the next update event TOP APB Write TOPB TOPB...

Page 585: ...upports two channels but if a third channel Z terminal is available this can be connected to an external interrupt and trigger a counter reset from the interrupt service routine By connecting a periodic signal from another timer as input capture on Compare Capture Channel 2 it is also possible to calculate speed and acceleration Note In Quadrature Decoder mode overflow and underflow triggers an up...

Page 586: ... 5 6 7 8 3 4 5 6 7 2 8 Figure 18 8 TIMER X2 Decoding Mode 18 3 1 11 X4 Decoding Mode In X4 Decoding mode the counter increments or decrements on every edge of Channel A and Channel B see Figure 18 9 TIMER X4 Decoding Mode on page 585 and Table 18 2 TIMER Counter Response in X4 Decoding Mode on page 585 Table 18 2 TIMER Counter Response in X4 Decoding Mode Opposite Channel Channel A Channel B Risin...

Page 587: ...pare Capture channels 0 and 1 are the inputs for the Quadrature Decoder Mode The input channel can be filtered before it is used which requires the input to remain stable for 5 cycles in a row before the input is propagated to the output TIMn_CCx PRS channels PRSSEL INSEL Filter FILT ICEDGE Input Capture x Figure 18 11 TIMER Input Pin Logic 18 3 2 2 Compare Capture Registers The Compare Capture ch...

Page 588: ...CV from TIMERn_CCx_CCVB if it contains valid data The CC value can be read without altering the FIFO contents by reading TIMERn_CCx_CCVP TIMERn_CCx_CCVB can also be read without altering the FIFO contents The ICV flag in TIMERn_STATUS indicates if there is a valid unread capture in TIMERn_CCx_CCV In this mode TIMERn_CCx_CCV is read only In the case where a capture is triggered while both TIMERn_CC...

Page 589: ...period capture the Compare Capture Channel should then be set to input capture on a rising edge of the same input signal To capture the width of a high pulse the Com pare Capture Channel should be set to capture on a falling edge of the input signal To measure the low pulse width of a signal oppo site polarities should be chosen 0 Input CNT Clear Start Input Capture frequency capture Input Capture...

Page 590: ... to allow for full 0 to 100 PWM generation Each example contains a high detail dia gram whcih specifies the exact timing of events durring Compare or PWM operation If occurring in the same cycle match action will have priority over overflow or underflow action The input selected through PRSSEL INSEL and FILTSEL in TIMERn_CCx_CTRL for the CC channel will also be sampled on com pare match and the re...

Page 591: ... to TIMERn_CCx_CCV on the next update event This functionality en sures glitch free PWM outputs The CCVBV flag in TIMERn_STATUS indicates whether the TIMERn_CCx_CCVB register contains data that has not yet been written to the TIMERn_CCx_CCV register Note that when writing 0 to TIMERn_CCx_CCVB in up down count mode the CCV value is updated when the timer counts from 0 to 1 Thus the compare match fo...

Page 592: ...RCLK 2 PRESC 1 x TOP 1 x 2 Figure 18 18 TIMER Up count Frequency Generation Equation The figure below provides cycle accurate timing and event genration information for frequency generation 0 TIMERn_TOP TIMERn_CCx_CCV 1 2 3 4 TIMERn_CCx Figure 18 19 TIMER Up count Frequency Generation Detail 18 3 2 8 Pulse Width Modulation PWM In PWM mode TIMERn_CCx_CCV is buffered to avoid glitches in the output ...

Page 593: ...update Figure 18 20 TIMER Up count PWM Generation RPWMup log TOP 1 log 2 Figure 18 21 TIMER Up count PWM Resolution Equation The PWM frequency is given by Figure 18 22 TIMER Up count PWM Frequency Equation on page 592 fPWMup down fHFPERCLK 2 PRESC x TOP 1 Figure 18 22 TIMER Up count PWM Frequency Equation The high duty cycle is given by Figure 18 23 TIMER Up count Duty Cycle Equation on page 592 D...

Page 594: ...mode Figure 18 26 TIMER 2x PWM Resolution Equation on page 593 RPWM2xmode log TOP 2 1 log 2 Figure 18 26 TIMER 2x PWM Resolution Equation The PWM frequency is given by Figure 18 27 TIMER 2x Mode PWM Frequency Equation Up count on page 593 fPWM2xmode fHFPERCLK floor TOP 2 1 Figure 18 27 TIMER 2x Mode PWM Frequency Equation Up count The high duty cycle is given by Figure 18 28 TIMER 2x Mode Duty Cyc...

Page 595: ...lution Equation The PWM frequency is given by Figure 18 31 TIMER Up Down count PWM Frequency Equation on page 594 fPWMup down fHFPERCLK 2 PRESC 1 x TOP Figure 18 31 TIMER Up Down count PWM Frequency Equation The high duty cycle is given by Figure 18 32 TIMER Up Down count Duty Cycle Equation on page 594 DSup down CCVx TOP Figure 18 32 TIMER Up Down count Duty Cycle Equation The figure below provid...

Page 596: ... CCVx values Figure 18 37 TIMER 2x Mode Duty Cycle Equation for CCVx 1 or CCVx even on page 595 and Figure 18 38 TIMER 2x Mode Duty Cycle Equation for all other CCVx odd values on page 595 DS2xmode CCVx 2 floor TOP 2 4 Figure 18 37 TIMER 2x Mode Duty Cycle Equation for CCVx 1 or CCVx even DS2xmode CCVx 2 CCVx floor TOP 2 4 Figure 18 38 TIMER 2x Mode Duty Cycle Equation for all other CCVx odd value...

Page 597: ...18 40 TIMER Triple Half Bridge on page 596 Transistors used in such a bridge often do not open close instan taneously and using the exact complementary inputs for the high and low side of a half bridge may result in situations where both gates are open This can give unnecessary current draw and short circuit the power supply The DTI unit provides dead time insertion to deal with this problem UH VH...

Page 598: ...g edge dead times share prescaler value The prescaler divides the HFPERCLKTIMERn by a configurable factor between 1 and 1024 which is set in the DTPRESC field in TIMER0_DTTIME The rising and falling edge dead times are configured in DTRISET and DTFALLT in TIM ER0_DTTIME to any number between 1 64 HFPERCLKTIMER0 cycles The DTAR and DTFATS bits in TIMER0_DTCTRL control the DTI output behavior when t...

Page 599: ...18 3 DTI output when timer halted DTAR DTFATS State 0 0 frozen 0 1 safe 1 0 running 1 1 running EFM32JG1 Reference Manual TIMER Timer Counter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 598 ...

Page 600: ...puts are active low This can be accomplished by manipulating the DTCINV bit of the TIMER0_DTCTRL register which inverts the polarity of the complementary outputs relative to the primary outputs DTIPOL 0 and DTCINV 0 results in outputs with opposite phase and active high states Figure 18 43 TIMER DTI Example 1 DTIPOL 1 and DTCINV 1 results in outputs with equal phase The primary output will be acti...

Page 601: ...and the outputs from the DTI unit are set to a well defined state The following options are available and can be enabled by configuring DTFACT in TIMER0_DTFC Set outputs to inactive level Clear outputs Tristate outputs With the first option enabled the output state in case of a fault depends on the polarity settings for the individual outputs An output set to be active high will be set low if a fa...

Page 602: ... met see Table 18 4 TIMER DMA Events on page 601 Events which clear the DMA requests do not clear interrupt flags Software must still manaually clear the interrupt flag if interrupts are in use If DMACLRACT is set in TIMERn_CTRL the DMA request is cleared when the triggered DMA channel is active without having to ac cess any timer registers This is usfull in cases where a timer event is used to tr...

Page 603: ...ister 0x064 TIMERn_CC0_CCV RWH a CC Channel Value Register 0x068 TIMERn_CC0_CCVP R CC Channel Value Peek Register 0x06C TIMERn_CC0_CCVB RWH CC Channel Buffer Register TIMERn_CCx_CTRL RW CC Channel Control Register TIMERn_CCx_CCV RWH a CC Channel Value Register TIMERn_CCx_CCVP R CC Channel Value Peek Register TIMERn_CCx_CCVB RWH CC Channel Buffer Register 0x090 TIMERn_CC3_CTRL RW CC Channel Control...

Page 604: ...17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0x0 0x0 0 0x0 0x0 0 0 0 0 0 0x0 Access RW RW RW RW RW RW RW RW RW RW RW RW RW Name RSSCOIST ATI PRESC CLKSEL X2CNT FALLA RISEA DMACLRACT DEBUGRUN QDM OSMEN SYNC MODE EFM32JG1 Reference Manual TIMER Timer Counter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 603 ...

Page 605: ... is divided by 512 10 DIV1024 The HFPERCLK is divided by 1024 23 18 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 17 16 CLKSEL 0x0 RW Clock Source Select These bits select the clock source for the timer Value Mode Description 0 PRESCHFPERCLK Prescaled HFPERCLK 1 CC1 Compare Capture Channel 1 Input 2 TIMEROUF Timer is clocked by und...

Page 606: ...in debug mode 1 Timer is running in debug mode 5 QDM 0 RW Quadrature Decoder Mode Selection This bit sets the mode for the quadrature decoder Value Mode Description 0 X2 X2 mode selected 1 X4 X4 mode selected 4 OSMEN 0 RW One shot Mode Enable Enable disable one shot mode 3 SYNC 0 RW Timer Start Stop Reload Synchronization When this bit is set the Timer is started stopped reloaded by start stop rel...

Page 607: ...19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 Access W1 W1 Name STOP START Bit Name Reset Access Description 31 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 1 STOP 0 W1 Stop Timer Set this bit to stop timer 0 START 0 W1 Start Timer Set this bit to start timer EFM32JG1 Reference Manual TIMER Timer Counter silabs com...

Page 608: ... 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access R R R R R R R R R R R R R R R Name CCPOL3 CCPOL2 CCPOL1 CCPOL0 ICV3 ICV2 ICV1 ICV0 CCVBV3 CCVBV2 CCVBV1 CCVBV0 TOPBV DIR RUNNING EFM32JG1 Reference Manual TIMER Timer Counter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 607 ...

Page 609: ... in TIMERn_CC1_CCV In Compare PWM mode this bit indicates the polarity of the selected input to CC channel 1 These bits are cleared when CCMODE is written to 0b00 Off Value Mode Description 0 LOWRISE CC1 polarity low level rising edge 1 HIGHFALL CC1 polarity high level falling edge 24 CCPOL0 0 R CC0 Polarity In Input Capture mode this bit indicates the polarity of the edge that triggered capture i...

Page 610: ...ontain a valid capture value FIFO emp ty 1 TIMERn_CC0_CCV contains a valid capture value FIFO not empty 15 12 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 11 CCVBV3 0 R CC3 CCVB Valid This field indicates that the TIMERn_CC3_CCVB registers contain data which have not been written to TIMERn_CC3_CCV These bits are only used in outpu...

Page 611: ...cription 0 TIMERn_CC0_CCVB does not contain valid data 1 TIMERn_CC0_CCVB contains valid data which will be written to TIMERn_CC0_CCV on the next update event 7 3 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 2 TOPBV 0 R TOPB Valid This indicates that TIMERn_TOPB contains valid data that has not been written to TIMERn_TOP This bit i...

Page 612: ...ure Buffer Overflow Interrupt Flag This bit indicates that a new capture value has pushed an unread value out of TIMERn_CC0_CCVB 7 CC3 0 R CC Channel 3 Interrupt Flag This bit indicates that there has been an interrupt event on Compare Capture channel 3 6 CC2 0 R CC Channel 2 Interrupt Flag This bit indicates that there has been an interrupt event on Compare Capture channel 2 5 CC1 0 R CC Channel ...

Page 613: ... 1 to set the ICBOF1 interrupt flag 8 ICBOF0 0 W1 Set ICBOF0 Interrupt Flag Write 1 to set the ICBOF0 interrupt flag 7 CC3 0 W1 Set CC3 Interrupt Flag Write 1 to set the CC3 interrupt flag 6 CC2 0 W1 Set CC2 Interrupt Flag Write 1 to set the CC2 interrupt flag 5 CC1 0 W1 Set CC1 Interrupt Flag Write 1 to set the CC1 interrupt flag 4 CC0 0 W1 Set CC0 Interrupt Flag Write 1 to set the CC0 interrupt ...

Page 614: ...9 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 0 0 0 Access R W1 R W1 R W1 R W1 R W1 R W1 R W1 R W1 R W1 R W1 R W1 Name ICBOF3 ICBOF2 ICBOF1 ICBOF0 CC3 CC2 CC1 CC0 DIRCHG UF OF EFM32JG1 Reference Manual TIMER Timer Counter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 613 ...

Page 615: ...2 Interrupt Flag Write 1 to clear the CC2 interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 5 CC1 0 R W1 Clear CC1 Interrupt Flag Write 1 to clear the CC1 interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 4 CC0 0 R W1 ...

Page 616: ...Interrupt Enable Enable disable the ICBOF1 interrupt 8 ICBOF0 0 RW ICBOF0 Interrupt Enable Enable disable the ICBOF0 interrupt 7 CC3 0 RW CC3 Interrupt Enable Enable disable the CC3 interrupt 6 CC2 0 RW CC2 Interrupt Enable Enable disable the CC2 interrupt 5 CC1 0 RW CC1 Interrupt Enable Enable disable the CC1 interrupt 4 CC0 0 RW CC0 Interrupt Enable Enable disable the CC0 interrupt 3 Reserved To...

Page 617: ...e bits hold the TOP value for the counter 18 5 9 TIMERn_TOPB Counter Top Value Buffer Register Offset Bit Position 0x020 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 Access RW Name TOPB Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 15 0 TO...

Page 618: ... 0x0000 Access RWH Name TIMERLOCKKEY Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 15 0 TIMERLOCKKEY 0x0000 RWH Timer Lock Key Write any other value than the unlock code to lock TIMERn_CTRL TIMERn_CMD TIMERn_TOP TIMERn_CNT TIMERn_CCx_CTRL and TIMERn_CCx_CCV from editing Write the unlock code ...

Page 619: ... Enable disable CC channel 1 complementary dead time insertion output connection to pin 8 CDTI0PEN 0 RW CC Channel 0 Complementary Dead Time Insertion Pin Enable Enable disable CC channel 0 complementary dead time insertion output connection to pin 7 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 3 CC3PEN 0 RW CC Channel 3 Pin Ena...

Page 620: ...34 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 0x00 0x00 0x00 Access RW RW RW RW Name CC3LOC CC2LOC CC1LOC CC0LOC EFM32JG1 Reference Manual TIMER Timer Counter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 619 ...

Page 621: ...cation 8 9 LOC9 Location 9 10 LOC10 Location 10 11 LOC11 Location 11 12 LOC12 Location 12 13 LOC13 Location 13 14 LOC14 Location 14 15 LOC15 Location 15 16 LOC16 Location 16 17 LOC17 Location 17 18 LOC18 Location 18 19 LOC19 Location 19 20 LOC20 Location 20 21 LOC21 Location 21 22 LOC22 Location 22 23 LOC23 Location 23 24 LOC24 Location 24 25 LOC25 Location 25 26 LOC26 Location 26 27 LOC27 Locatio...

Page 622: ...cation 8 9 LOC9 Location 9 10 LOC10 Location 10 11 LOC11 Location 11 12 LOC12 Location 12 13 LOC13 Location 13 14 LOC14 Location 14 15 LOC15 Location 15 16 LOC16 Location 16 17 LOC17 Location 17 18 LOC18 Location 18 19 LOC19 Location 19 20 LOC20 Location 20 21 LOC21 Location 21 22 LOC22 Location 22 23 LOC23 Location 23 24 LOC24 Location 24 25 LOC25 Location 25 26 LOC26 Location 26 27 LOC27 Locatio...

Page 623: ...ation 8 9 LOC9 Location 9 10 LOC10 Location 10 11 LOC11 Location 11 12 LOC12 Location 12 13 LOC13 Location 13 14 LOC14 Location 14 15 LOC15 Location 15 16 LOC16 Location 16 17 LOC17 Location 17 18 LOC18 Location 18 19 LOC19 Location 19 20 LOC20 Location 20 21 LOC21 Location 21 22 LOC22 Location 22 23 LOC23 Location 23 24 LOC24 Location 24 25 LOC25 Location 25 26 LOC26 Location 26 27 LOC27 Location...

Page 624: ...tion 8 9 LOC9 Location 9 10 LOC10 Location 10 11 LOC11 Location 11 12 LOC12 Location 12 13 LOC13 Location 13 14 LOC14 Location 14 15 LOC15 Location 15 16 LOC16 Location 16 17 LOC17 Location 17 18 LOC18 Location 18 19 LOC19 Location 19 20 LOC20 Location 20 21 LOC21 Location 21 22 LOC22 Location 22 23 LOC23 Location 23 24 LOC24 Location 24 25 LOC25 Location 25 26 LOC26 Location 26 27 LOC27 Location ...

Page 625: ...n 0x03C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 0x00 0x00 Access RW RW RW Name CDTI2LOC CDTI1LOC CDTI0LOC EFM32JG1 Reference Manual TIMER Timer Counter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 624 ...

Page 626: ...Location 8 9 LOC9 Location 9 10 LOC10 Location 10 11 LOC11 Location 11 12 LOC12 Location 12 13 LOC13 Location 13 14 LOC14 Location 14 15 LOC15 Location 15 16 LOC16 Location 16 17 LOC17 Location 17 18 LOC18 Location 18 19 LOC19 Location 19 20 LOC20 Location 20 21 LOC21 Location 21 22 LOC22 Location 22 23 LOC23 Location 23 24 LOC24 Location 24 25 LOC25 Location 25 26 LOC26 Location 26 27 LOC27 Locat...

Page 627: ...ocation 8 9 LOC9 Location 9 10 LOC10 Location 10 11 LOC11 Location 11 12 LOC12 Location 12 13 LOC13 Location 13 14 LOC14 Location 14 15 LOC15 Location 15 16 LOC16 Location 16 17 LOC17 Location 17 18 LOC18 Location 18 19 LOC19 Location 19 20 LOC20 Location 20 21 LOC21 Location 21 22 LOC22 Location 22 23 LOC23 Location 23 24 LOC24 Location 24 25 LOC25 Location 25 26 LOC26 Location 26 27 LOC27 Locati...

Page 628: ...cation 8 9 LOC9 Location 9 10 LOC10 Location 10 11 LOC11 Location 11 12 LOC12 Location 12 13 LOC13 Location 13 14 LOC14 Location 14 15 LOC15 Location 15 16 LOC16 Location 16 17 LOC17 Location 17 18 LOC18 Location 18 19 LOC19 Location 19 20 LOC20 Location 20 21 LOC21 Location 21 22 LOC22 Location 22 23 LOC23 Location 23 24 LOC24 Location 24 25 LOC25 Location 25 26 LOC26 Location 26 27 LOC27 Locatio...

Page 629: ... 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0x0 0x0 0x0 0x0 0x0 0x0 0 0 0x0 Access RW RW RW RW RW RW RW RW RW RW RW RW Name FILT INSEL PRSCONF ICEVCTRL ICEDGE PRSSEL CUFOA COFOA CMOA COIST OUTINV MODE EFM32JG1 Reference Manual TIMER Timer Counter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 628 ...

Page 630: ...errupt flag is set DMA request however is set on every capture Value Mode Description 0 EVERYEDGE PRS output pulse and interrupt flag set on every capture 1 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 2 RISING PRS output pulse and interrupt flag set on rising edge only if ICEDGE BOTH 3 FALLING PRS output pulse and interrupt flag set on falling edge only if ICEDG...

Page 631: ...with future devices always write bits to 0 More information in 1 2 Conven tions 13 12 CUFOA 0x0 RW Counter Underflow Output Action Select output action on counter underflow Value Mode Description 0 NONE No action on counter underflow 1 TOGGLE Toggle output on counter underflow 2 CLEAR Clear output on counter underflow 3 SET Set output on counter underflow 11 10 COFOA 0x0 RW Counter Overflow Output...

Page 632: ...W CC Channel Mode These bits select the mode for Compare Capture channel Value Mode Description 0 OFF Compare Capture channel turned off 1 INPUTCAPTURE Input capture 2 OUTPUTCOMPARE Output compare 3 PWM Pulse Width Modulation 18 5 16 TIMERn_CCx_CCV CC Channel Value Register Actionable Reads Offset Bit Position 0x064 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 ...

Page 633: ...osition 0x06C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 Access RWH Name CCVB Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 15 0 CCVB 0x0000 RWH CC Channel Value Buffer In Input Capture mode this field holds the last capture value if the...

Page 634: ...24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0x0 0 0 0 0 Access RW RW RW RW RW RW RW RW Name DTPRSEN DTFATS DTAR DTPRSSEL DTCINV DTIPOL DTDAS DTEN EFM32JG1 Reference Manual TIMER Timer Counter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 633 ...

Page 635: ...patibility with future devices always write bits to 0 More information in 1 2 Conven tions 7 4 DTPRSSEL 0x0 RW DTI PRS Source Channel Select Selects which PRS channel compare chanel 0 will listen to Value Mode Description 0 PRSCH0 PRS Channel 0 selected as input 1 PRSCH1 PRS Channel 1 selected as input 2 PRSCH2 PRS Channel 2 selected as input 3 PRSCH3 PRS Channel 3 selected as input 4 PRSCH4 PRS C...

Page 636: ...t Access Description 1 RESTART DTI restart on debugger exit 0 DTEN 0 RW DTI Enable Enable disable DTI EFM32JG1 Reference Manual TIMER Timer Counter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 635 ...

Page 637: ...RW DTI Rise time Set time span for the rising edge Value Description DTRISET Rise time of DTRISET 1 prescaled HFPERCLK cycles 7 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 3 0 DTPRESC 0x0 RW DTI Prescaler Setting Select prescaler for DTI Value Mode Description 0 DIV1 The HFPERCLK is undivided 1 DIV2 The HFPERCLK is divided by 2...

Page 638: ...4 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0x0 0x0 0x0 Access RW RW RW RW RW RW RW Name DTLOCKUPFEN DTDBGFEN DTPRS1FEN DTPRS0FEN DTFA DTPRS1FSEL DTPRS0FSEL EFM32JG1 Reference Manual TIMER Timer Counter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 637 ...

Page 639: ...puts 3 TRISTATE Tristate outputs 15 12 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 11 8 DTPRS1FSEL 0x0 RW DTI PRS Fault Source 1 Select Select PRS channel for fault source 1 Value Mode Description 0 PRSCH0 PRS Channel 0 selected as fault source 1 1 PRSCH1 PRS Channel 1 selected as fault source 1 2 PRSCH2 PRS Channel 2 selected as...

Page 640: ...ault source 3 4 PRSCH4 PRS Channel 4 selected as fault source 4 5 PRSCH5 PRS Channel 5 selected as fault source 5 6 PRSCH6 PRS Channel 6 selected as fault source 6 7 PRSCH7 PRS Channel 7 selected as fault source 7 8 PRSCH8 PRS Channel 8 selected as fault source 8 9 PRSCH9 PRS Channel 9 selected as fault source 9 10 PRSCH10 PRS Channel 10 selected as fault source 10 11 PRSCH11 PRS Channel 11 select...

Page 641: ... the DTI 4 DTOGCDTI1EN 0 RW DTI CDTI1 Output Generation Enable This bit enables disables output generation for the CDTI1 output from the DTI 3 DTOGCDTI0EN 0 RW DTI CDTI0 Output Generation Enable This bit enables disables output generation for the CDTI0 output from the DTI 2 DTOGCC2EN 0 RW DTI CC2 Output Generation Enable This bit enables disables output generation for the CC2 output from the DTI 1...

Page 642: ... to 1 The TIMER0_DTFAULTC register can be used to clear fault bits 2 DTDBGF 0 R DTI Debugger Fault This bit is set to 1 if a debugger fault has occurred and DTDBGFEN is set to 1 The TIMER0_DTFAULTC register can be used to clear fault bits 1 DTPRS1F 0 R DTI PRS 1 Fault This bit is set to 1 if a PRS 1 fault has occurred and DTPRS1FEN is set to 1 The TIMER0_DTFAULTC register can be used to clear faul...

Page 643: ...future devices always write bits to 0 More information in 1 2 Conven tions 3 TLOCKUPFC 0 W1 DTI Lockup Fault Clear Write 1 to this bit to clear core lockup fault 2 DTDBGFC 0 W1 DTI Debugger Fault Clear Write 1 to this bit to clear debugger fault 1 DTPRS1FC 0 W1 DTI PRS1 Fault Clear Write 1 to this bit to clear PRS 1 fault 0 DTPRS0FC 0 W1 DTI PRS0 Fault Clear Write 1 to this bit to clear PRS 0 faul...

Page 644: ...EY 0x0000 RWH DTI Lock Key Write any other value than the unlock code to lock TIMER0_ROUTE TIMER0_DTCTRL TIMER0_DTTIME and TIM ER0_DTFC from editing Write the unlock code to unlock When reading the register bit 0 is set when the lock is enabled Mode Value Description Read Operation UNLOCKED 0 TIMER DTI registers are unlocked LOCKED 1 TIMER DTI registers are locked Write Operation LOCK 0 Lock TIMER...

Page 645: ...st of the device is powered down allowing simple tasks to be performed while the power consumption of the system is kept at an absolute minimum The LETIMER can be used to output a variety of waveforms with minimal software intervention It can also be connected to the Real Time Counter RTC using PRS and can be configured to start counting on compare matches from the RTC 19 2 Features 16 bit down co...

Page 646: ... Clear Figure 19 1 LETIMER Overview 19 3 1 Timer The timer is started by setting command bit START in LETIMERn_CMD and stopped by setting the STOP command bit in the same register RUNNING in LETIMERn_STATUS is set as long as the timer is running The timer can also be started on external signals such as a compare match from the Real Time Counter If START and STOP are set at the same time STOP has p...

Page 647: ...of the operation of the timer including defining the number of times the counter should wrap around Four different repeat modes are available see Table 19 1 LETIMER Repeat Modes on page 646 Table 19 1 LETIMER Repeat Modes REPMODE Mode Description 0b00 Free running The timer runs until it is stopped 0b01 One shot The timer runs as long as LETI MERn_REP0 0 LETIMERn_REP0 is de cremented at each timer...

Page 648: ...for positive clock edge If COMP0TOP TOP COMP0 Else TOP 0xFFFF TOP Figure 19 2 LETIMER State Machine for Free running Mode Note that the CLEAR command bit in LETIMERn_CMD always has priority over other changes to LETIMERn_CNT When the clear command is used LETIMERn_CNT is set to 0 and an underflow event will not be generated when LETIMERn_CNT wraps around to the top value or 0xFFFF Since no underfl...

Page 649: ...urs the timer decrement will not occur and the new value is assigned LETIMERn_REP0 can be written while the timer is running to allow the timer to run for longer periods at a time without stopping Figure 19 3 LETIMER One shot Repeat State Machine on page 648 RUNNING YES CNT 0 CNT CNT 1 NO REP0 2 YES NO STOP 1 REP0 0 CNT TOP If START REP0 REP0 1 If STOP RUNNING 0 Else if START RUNNING 1 End if STAR...

Page 650: ...imes with period 200 then 3 times with period 50 A state machine for the buffered repeat mode is shown in Figure 19 4 LETIMER Buffered Repeat State Machine on page 649 REP1USED shown in the state machine is an internal variable that keeps track of whether the value in LETIMERn_REP1 has been loa ded into LETIMERn_REP0 or not The purpose of this is that a value written to LETIMERn_REP1 should only b...

Page 651: ...same time The state machine for this repeat mode can be seen in Figure 19 5 LETIMER Double Repeat State Machine on page 650 RUNNING YES CNT 0 CNT CNT 1 NO REP0 2 And REP1 2 YES NO STOP 1 REP0 0 CNT TOP If REP0 0 REP0 REP0 1 If REP1 0 REP1 REP1 1 If STOP RUNNING 0 Else if START RUNNING 1 End if START 0 STOP 0 Wait for positive clock edge YES If COMP0TOP TOP COMP0 Else TOP 0xFFFF TOP NO START YES CN...

Page 652: ...11 0 PRSSTOPSEL LFACLKLETIMERn Syncronizer Edge Detect PRSSTOPMODE None Rising Falling Both PRS_STOP PRS_IN 11 0 PRSCLEARSEL LFACLKLETIMERn Syncronizer Edge Detect PRSCLEARMODE None Rising Falling Both PRS_CLEAR PRSSTARTEN PRSSTOPEN PRSCLEAREN Figure 19 7 LETIMER PRS input triggers 19 3 3 9 Debug If DEBUGRUN in LETIMERn_CTRL is cleared the LETIMER automatically stops counting when the CPU is halte...

Page 653: ...state of the corresponding LETIMERn_REPx registers They will only be set active if the LETIMERn_REPx registers are nonzero however Note For free running mode LETIMERn_REP0 0 for output generation to be enabled The polarity of the outputs can be set individually by configuring OPOL0 and OPOL1 in LETIMERn_CTRL When these are cleared their respective outputs have a low idle value and a high active va...

Page 654: ...erated on the output CNT COMP0 3 3 3 2 3 1 3 0 3 3 3 2 3 1 3 0 3 3 3 2 3 1 3 0 Initial configuration UFIF UFIF UFIF Int flags set LFACLKLETIMERn LETn_O0 UFOA0 01 LETn_O0 UFOA0 10 LETn_O0 UFOA0 00 REP0 3 3 3 3 2 2 2 2 1 1 1 1 Stop REP0IF 3 0 0 3 0 0 3 0 0 3 0 0 3 0 0 3 0 0 3 0 0 3 0 0 3 0 0 3 0 0 3 0 0 3 0 0 3 0 3 Figure 19 9 LETIMER Repeated Counting Using the Double repeat mode output can be gene...

Page 655: ...l 0 and LETn_O1 can be rout ed to PRS channel 1 Enabling the PRS connection can be done by setting SOURCESEL to LETIMERx and SIGSEL to LETIMERxCHn in PRS_CHx_CTRL The PRS register description can be found in 13 5 Register Description 19 3 6 Examples This section presents a couple of usage examples for the LETIMER EFM32JG1 Reference Manual LETIMER Low Energy Timer silabs com Smart Connected Energy ...

Page 656: ...not have to update the registers between each pulse train For the example in Figure 19 11 LETIMER Triggered Operation on page 655 the initial values cause the LETIMER to generate two pulses with 3 cycle periods or a single pulse 3 cycles wide every time the LETIMER is started After the output has been generated the LETIMER stops and is ready to be triggered again CNT TOP0 TOP1 REP0 REP1 2 X 0 0 2 ...

Page 657: ...flags set Stop final values Write COMP1 2 REP1 2 UFIF UFIF UFIF REP0IF 4 4 4 4 4u 4u 4u 2 2 2u 2u 2u 2u 2 2 1 1 2 2 0 1 2u 2u REP0IF LFACLKLETIMERn LETn_O0 UFOA0 01 LETn_O1 UFOA0 10 Pulse Seq 1 Pulse Seq 2 Pulse Seq 3 4 4 4 4 4 4 2 2 2 2 2 0 0 2u Figure 19 12 LETIMER Continuous Operation The first two sequences are loaded into the LETIMER before the timer is started LETIMERn_COMP0 is set to 2 cycl...

Page 658: ...ERn_CNT Not Initialized to 0 19 3 6 3 PWM Output There are several ways of generating PWM output with the LETIMER but the most straight forward way is using the PWM output mode This mode is enabled by setting UFOA0 or UFOA1 in LETIMERn_CTRL to 3 In PWM mode the output is set idle on timer un derflow and active on LETIMERn_COMP1 match so if for instance COMP0TOP 1 and OPOL0 0 in LETIMERn_CTRL LETI ...

Page 659: ...are Value Register 0 0x014 LETIMERn_COMP1 RW Compare Value Register 1 0x018 LETIMERn_REP0 RWH Repeat Counter Register 0 0x01C LETIMERn_REP1 RWH Repeat Counter Register 1 0x020 LETIMERn_IF R Interrupt Flag Register 0x024 LETIMERn_IFS W1 Interrupt Flag Set Register 0x028 LETIMERn_IFC R W1 Interrupt Flag Clear Register 0x02C LETIMERn_IEN RW Interrupt Enable Register 0x034 LETIMERn_SYNCBUSY R Synchron...

Page 660: ...ronous Registers Offset Bit Position 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0x0 0x0 0x0 Access RW RW RW RW RW RW RW RW Name DEBUGRUN COMP0TOP BUFTOP OPOL1 OPOL0 UFOA1 UFOA0 REPMODE EFM32JG1 Reference Manual LETIMER Low Energy Timer silabs com Smart Connected Energy friendly Preliminary Rev 0 6 659 ...

Page 661: ...red top value Value Description 0 COMP0 is only written by software 1 COMP0 is set to COMP1 when REP0 reaches 0 7 OPOL1 0 RW Output 1 Polarity Defines the idle value of output 1 6 OPOL0 0 RW Output 0 Polarity Defines the idle value of output 0 5 4 UFOA1 0x0 RW Underflow Output Action 1 Defines the action on LETn_O1 on a LETIMER underflow Value Mode Description 0 NONE LETn_O1 is held at its idle va...

Page 662: ...BLE Both REP0 and REP1 are decremented when the LETIMER wraps around The LETIMER counts until both REP0 and REP1 are zero 19 5 2 LETIMERn_CMD Command Register Offset Bit Position 0x004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 Access W1 W1 W1 W1 W1 Name CTO1 CTO0 CLEAR STOP START Bit Name Reset Access Description 31 5 Reserved To ensure c...

Page 663: ...Set when LETIMER is running 19 5 4 LETIMERn_CNT Counter Value Register Offset Bit Position 0x00C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 Access RWH Name CNT Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 15 0 CNT 0x0000 RWH Counter Val...

Page 664: ...e and optionally top value for LETIMER 19 5 6 LETIMERn_COMP1 Compare Value Register 1 Async Reg For More information about Registers please see 4 3 Access to Low Energy Peripherals Asynchronous Registers Offset Bit Position 0x014 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 Access RW Name COMP1 Bit Name Reset Access Description 31 16 Reserved T...

Page 665: ...ounter 0 Optional repeat counter 19 5 8 LETIMERn_REP1 Repeat Counter Register 1 Async Reg For More information about Registers please see 4 3 Access to Low Energy Peripherals Asynchronous Registers Offset Bit Position 0x01C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 Access RWH Name REP1 Bit Name Reset Access Description 31 8 Reserved To ensure ...

Page 666: ...0 R Repeat Counter 1 Interrupt Flag Set when repeat counter 1 reaches zero 3 REP0 0 R Repeat Counter 0 Interrupt Flag Set when repeat counter 0 reaches zero or when the REP1 interrupt flag is loaded into the REP0 interrupt flag 2 UF 0 R Underflow Interrupt Flag Set on LETIMER underflow 1 COMP1 0 R Compare Match 1 Interrupt Flag Set when LETIMER reaches the value of COMP1 0 COMP0 0 R Compare Match ...

Page 667: ...ts to 0 More information in 1 2 Conven tions 4 REP1 0 W1 Set REP1 Interrupt Flag Write 1 to set the REP1 interrupt flag 3 REP0 0 W1 Set REP0 Interrupt Flag Write 1 to set the REP0 interrupt flag 2 UF 0 W1 Set UF Interrupt Flag Write 1 to set the UF interrupt flag 1 COMP1 0 W1 Set COMP1 Interrupt Flag Write 1 to set the COMP1 interrupt flag 0 COMP0 0 W1 Set COMP0 Interrupt Flag Write 1 to set the C...

Page 668: ...upt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 2 UF 0 R W1 Clear UF Interrupt Flag Write 1 to clear the UF interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 1 COMP1 0 R W1 Clear COMP1 Interrupt Flag Write 1 to clear the C...

Page 669: ...COMP1 Interrupt Enable Enable disable the COMP1 interrupt 0 COMP0 0 RW COMP0 Interrupt Enable Enable disable the COMP0 interrupt 19 5 13 LETIMERn_SYNCBUSY Synchronization Busy Register Offset Bit Position 0x034 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 Access R Name CMD Bit Name Reset Access Description 31 2 Reserved To ensure compatibility with ...

Page 670: ... devices always write bits to 0 More information in 1 2 Conven tions 1 OUT1PEN 0 RW Output 1 Pin Enable When set output 1 of the LETIMER is enabled Value Description 0 The LETn_O1 pin is disabled 1 The LETn_O1 pin is enabled 0 OUT0PEN 0 RW Output 0 Pin Enable When set output 0 of the LETIMER is enabled Value Description 0 The LETn_O0 pin is disabled 1 The LETn_O0 pin is enabled EFM32JG1 Reference ...

Page 671: ... Position 0x044 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 0x00 Access RW RW Name OUT1LOC OUT0LOC EFM32JG1 Reference Manual LETIMER Low Energy Timer silabs com Smart Connected Energy friendly Preliminary Rev 0 6 670 ...

Page 672: ...Location 8 9 LOC9 Location 9 10 LOC10 Location 10 11 LOC11 Location 11 12 LOC12 Location 12 13 LOC13 Location 13 14 LOC14 Location 14 15 LOC15 Location 15 16 LOC16 Location 16 17 LOC17 Location 17 18 LOC18 Location 18 19 LOC19 Location 19 20 LOC20 Location 20 21 LOC21 Location 21 22 LOC22 Location 22 23 LOC23 Location 23 24 LOC24 Location 24 25 LOC25 Location 25 26 LOC26 Location 26 27 LOC27 Locat...

Page 673: ...cation 8 9 LOC9 Location 9 10 LOC10 Location 10 11 LOC11 Location 11 12 LOC12 Location 12 13 LOC13 Location 13 14 LOC14 Location 14 15 LOC15 Location 15 16 LOC16 Location 16 17 LOC17 Location 17 18 LOC18 Location 18 19 LOC19 Location 19 20 LOC20 Location 20 21 LOC21 Location 21 22 LOC22 Location 22 23 LOC23 Location 23 24 LOC24 Location 24 25 LOC25 Location 25 26 LOC26 Location 26 27 LOC27 Locatio...

Page 674: ... 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 0x0 0x0 0x0 0x0 0x0 Access RW RW RW RW RW RW Name PRSCLEARMODE PRSSTOPMODE PRSSTARTMODE PRSCLEARSEL PRSSTOPSEL PRSSTARTSEL EFM32JG1 Reference Manual LETIMER Low Energy Timer silabs com Smart Connected Energy friendly Preliminary Rev 0 6 673 ...

Page 675: ...S input can stop the LETIMER 3 BOTH Both the rising or falling edge of the selected PRS input can stop the LETIMER 21 20 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 19 18 PRSSTARTMODE 0x0 RW PRS Start Mode Determines mode for PRS input start Value Mode Description 0 NONE PRS cannot start the LETIMER 1 RISING Rising edge of select...

Page 676: ...RSCH3 PRS Channel 3 selected as input 4 PRSCH4 PRS Channel 4 selected as input 5 PRSCH5 PRS Channel 5 selected as input 6 PRSCH6 PRS Channel 6 selected as input 7 PRSCH7 PRS Channel 7 selected as input 8 PRSCH8 PRS Channel 8 selected as input 9 PRSCH9 PRS Channel 9 selected as input 10 PRSCH10 PRS Channel 10 selected as input 11 PRSCH11 PRS Channel 11 selected as input 5 4 Reserved To ensure compa...

Page 677: ...ected as input 8 PRSCH8 PRS Channel 8 selected as input 9 PRSCH9 PRS Channel 9 selected as input 10 PRSCH10 PRS Channel 10 selected as input 11 PRSCH11 PRS Channel 11 selected as input EFM32JG1 Reference Manual LETIMER Low Energy Timer silabs com Smart Connected Energy friendly Preliminary Rev 0 6 676 ...

Page 678: ...it counter which operates on a low frequency oscillator and is capable of running in all Energy Modes It can provide periodic Wakeup events and PRS signals which can be used to wake up peripherals from any energy mode The CRYOTIMER provides a very wide range of periods for the interrupts facilitating flexible ultra low energy operation Because of its simplicity the CRYOTIMER is a lower energy solu...

Page 679: ...view on page 678 Interrupt Wakeup Event Counter PRS Prescaler PRESC PERIODSEL Edge Detector LFXO LFRCO ULFRCO CRYOCLK OSCSEL Figure 20 1 CRYOTIMER Block Overview EFM32JG1 Reference Manual CRYOTIMER Ultra Low Energy Timer Counter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 678 ...

Page 680: ...µs 36 4 hours DIV2 61 µs 72 8 hours DIV4 122 µs 145 6 hours DIV8 244 µs 12 days DIV16 488 µs 24 days DIV32 977 µs 48 days DIV64 1 95 ms 97 days DIV128 3 91 ms 194 days The 32 bit counter value of the CRYOTIMER can be read using the CRYOTIMER_CNT register The PRS output pulses of the CRYOTIMER are 1 CRYOCLK clock cycle wide However if the PRESC and PERIODSEL are both set to 0 the width of these pul...

Page 681: ...008 CRYOTIMER_CNT R Counter Value 0x00C CRYOTIMER_EM4WUEN RW Wake Up Enable 0x010 CRYOTIMER_IF R Interrupt Flag Register 0x014 CRYOTIMER_IFS W1 Interrupt Flag Set Register 0x018 CRYOTIMER_IFC R W1 Interrupt Flag Clear Register 0x01C CRYOTIMER_IEN RW Interrupt Enable Register EFM32JG1 Reference Manual CRYOTIMER Ultra Low Energy Timer Counter silabs com Smart Connected Energy friendly Preliminary Re...

Page 682: ...6 DIV64 LF Oscillator frequency divided by 64 7 DIV128 LF Oscillator frequency divided by 128 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 3 2 OSCSEL 0x0 RW Select Low frequency oscillator These bits select the low frequency oscillator for the CRYOTIMER operation This field should be set after the oscillator to be selected is re...

Page 683: ...on 0x004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x20 Access RW Name PERIODSEL EFM32JG1 Reference Manual CRYOTIMER Ultra Low Energy Timer Counter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 682 ...

Page 684: ...cles 13 Wakeup event after 8k Pre scaled clock cycles 14 Wakeup event after 16k Pre scaled clock cycles 15 Wakeup event after 32k Pre scaled clock cycles 16 Wakeup event after 64k Pre scaled clock cycles 17 Wakeup event after 128k Pre scaled clock cycles 18 Wakeup event after 256k Pre scaled clock cycles 19 Wakeup event after 512k Pre scaled clock cycles 20 Wakeup event after 1M Pre scaled clock c...

Page 685: ...N Wake Up Enable Offset Bit Position 0x00C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 Access RW Name EM4WU Bit Name Reset Access Description 31 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 0 EM4WU 0 RW EM4 Wake up enable Write 1 to enable wake up request write 0 to disable wake ...

Page 686: ...Wakeup event Interrupt occurs 20 5 6 CRYOTIMER_IFS Interrupt Flag Set Register Offset Bit Position 0x014 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 Access W1 Name PERIOD Bit Name Reset Access Description 31 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 0 PERIOD 0 W1 Set PERIOD In...

Page 687: ... value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 20 5 8 CRYOTIMER_IEN Interrupt Enable Register Offset Bit Position 0x01C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 Access RW Name PERIOD Bit Name Reset Access Description 31 1 Reserved To ensure compatibility with future devices always write...

Page 688: ... or from external pins Response time and thereby the current consumption can be config ured by altering the current supply to the comparator 21 2 Features Up to 144 selectable external I O inputs for both positive and negative inputs Up to 48 I O can be used as a dividable reference Voltage supply monitoring Low power mode for internal V DD and bandgap references Selectable hysteresis 8 values Val...

Page 689: ...Dedicated APORT HYST0 DIVVA0 DIVVB0 HYST1 DIVVA1 DIVVB1 BIASPROG FULLBIAS CSRESEN CSRESSEL Figure 21 1 ACMP Overview The comparator has two analog inputs one positive and one negative When the comparator is active the output indicates which of the two input voltages is higher When the voltage on the positive input is higher than the voltage on the negative input the digital output is high and vice...

Page 690: ...tected EM1 can still be entered during warm up After the warm up period is completed interrupts will be detected in EM2 and EM3 21 3 2 Response Time There is a delay from when the input voltage changes polarity to when the output toggles This delay is called the response time and can be altered by increasing or decreasing the bias current to the comparator through the BIASPROG and FULLBIAS fields ...

Page 691: ...OSSEL NEGSEL HYST There are two hysteresis registers ACMPn_HYSTERESIS0 and ACMPn_HYSTERESIS1 as the ACMP supports asymmetric hystere sis ACMPn_HYSTERESIS0 are the hysteresis values used when the comparator output is 0 ACMPn_HYSTERESIS1 are the values used when the comparator output is 1 The user must set both registers to the same values if symmetric hysteresis is desired Along with the HYST field...

Page 692: ...mily of devices Refer to the Pin Definition and the APORT Client Map in the device datasheet for specific details on which I O are available for each family and package configuration Table 21 1 ACMP0 and ACMP1 Bus and Pin Mapping ACMP Port APORT0 APORT1 APORT2 APORT3 APORT4 Polarity X Y X Y X Y X Y X Y Shared Bus n a BUSAX BUSAY BUSBX BUSBY BUSCX BUSCY BUSDX BUSDY CH31 PB15 PB15 CH30 PB14 PB14 CH2...

Page 693: ...nternal voltages VADIV and VBDIV are two dividable voltages VADIV can be VDD divided or the user can choose to select inputs from a number of APORT buses VBDIV consists of two dividable band gap references of either 1 25V or 2 5V Each of these voltages have dividers in the ACMPn_HYSTERESIS0 1 registers The formula for the division of these voltages is VADIV VA DIVVA 1 64 Figure 21 3 VA Voltage Div...

Page 694: ...By measuring the output frequency with a timer via the PRS the change in capacitance can be detected The analog comparator contains a feedback loop including an optional internal resistor This resistor is enabled by setting the CSRE SEN bit in ACMPn_INPUTSEL The resistance can be set to any of 8 values by configuring the CSRESSEL bits in ACMPn_INPUTSEL The source for VADIV is set to VDD by setting...

Page 695: ...EN The edge interrupt can also be used to wake up the device from EM3 Stop EM1 Sleep The analog comparator includes the interrupt flag WARMUP in ACMPn_IF which is set when a warm up sequence has finished An interrupt request will be sent if the WARMUP interrupt flag in ACMPn_IF is set and enabled through the WARMUP bit in ACMPn_IEN The analog comparator can also generate an interrupt if a bus conf...

Page 696: ...l if the X or Y bus selected via POSSEL or NEGESEL is mastered or not APORTVMASTERDIS controls if either the X or Y bus selection of VASEL is mastered or not When bus mastering is disabled it is the other APORT client that determines which pin is connected to the APORT bus 21 3 9 Supply Voltage Monitoring The ACMP can be used to monitor supply voltages The ACMP can select which voltage it uses via...

Page 697: ...0 9 8 7 6 5 4 3 2 1 0 Reset 0 0x07 0 0 0x0 0 0x0 0 0 0 0 0 0 Access RW RW RW RW RW RW RW RW RW RW RW RW RW Name FULLBIAS BIASPROG IFALL IRISE INPUTRANGE ACCURACY PWRSEL APORTVMASTERDIS APORTYMASTERDIS APORTXMASTERDIS GPIOINV INACTVAL EN EFM32JG1 Reference Manual ACMP Analog Comparator silabs com Smart Connected Energy friendly Preliminary Rev 0 6 696 ...

Page 698: ...8 INPUTRANGE 0x0 RW Input Range Adjust performance of the comparator for a given input voltage range Value Mode Description 0 FULL Setting when the input can be from 0 to VDD 1 GTVDDDIV2 Setting when the input will always be greater than VDD 2 2 LTVDDDIV2 Setting when the input will always be less than VDD 2 17 16 Reserved To ensure compatibility with future devices always write bits to 0 More inf...

Page 699: ...be from another peripheral and the ACMP only passively looks at the bus When 1 the selection of channel for a selected bus is ignored the bus is not and is whatever selection the external device mas tering the bus has configured for the APORT bus Value Description 0 Bus mastering enabled 1 Bus mastering disabled 8 APORTXMASTER DIS 0 RW APORT Bus X Master Disable Determines if the ACMP will request...

Page 700: ...cription 0 LOW The inactive value is 0 1 HIGH The inactive state is 1 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 0 EN 0 RW Analog Comparator Enable Enable disable analog comparator EFM32JG1 Reference Manual ACMP Analog Comparator silabs com Smart Connected Energy friendly Preliminary Rev 0 6 699 ...

Page 701: ... 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 0 0 0 0x00 0x00 0x00 Access RW RW RW RW RW RW RW Name CSRESSEL CSRESEN VLPSEL VBSEL VASEL NEGSEL POSSEL EFM32JG1 Reference Manual ACMP Analog Comparator silabs com Smart Connected Energy friendly Preliminary Rev 0 6 700 ...

Page 702: ...r value 7 27 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 26 CSRESEN 0 RW Capacitive Sense Mode Internal Resistor Enable Enable disable the internal capacitive sense resistor 25 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 24 VLPSEL 0 RW Low Power Sampled Voltage ...

Page 703: ...1 APORT0XCH2 0x02 Dedicated APORT0X Channel 2 APORT0XCH15 0x0f Dedicated APORT0X Channel 15 APORT0YCH0 0x10 Dedicated APORT0Y Channel 0 APORT0YCH1 0x11 Dedicated APORT0Y Channel 1 APORT0YCH2 0x12 Dedicated APORT0Y Channel 2 APORT0YCH15 0x1f Dedicated APORT0Y Channel 15 APORT1XCH0 0x20 APORT1X Channel 0 APORT1YCH1 0x21 APORT1Y Channel 1 APORT1XCH2 0x22 APORT1X Channel 2 APORT1YCH3 0x23 APORT1Y Chan...

Page 704: ...81 APORT4X Channel 1 APORT4YCH2 0x82 APORT4Y Channel 2 APORT4XCH3 0x83 APORT4X Channel 3 APORT4YCH4 0x84 APORT4Y Channel 4 APORT4XCH5 0x85 APORT4X Channel 5 APORT4YCH30 0x9e APORT4Y Channel 30 APORT4XCH31 0x9f APORT4X Channel 31 DACOUT0 0xf2 DAC0 Output DACOUT1 0xf3 DAC1 Output VLP 0xfb Low Power Sampled Voltage VBDIV 0xfc Divided VB Voltage VADIV 0xfd Divided VA Voltage VDD 0xfe VDD as selected v...

Page 705: ...APORT2XCH1 0x41 APORT2X Channel 1 APORT2YCH2 0x42 APORT2Y Channel 2 APORT2XCH3 0x43 APORT2X Channel 3 APORT2YCH4 0x44 APORT2Y Channel 4 APORT2XCH5 0x45 APORT2X Channel 5 APORT2YCH30 0x5e APORT2Y Channel 30 APORT2XCH31 0x5f APORT2X Channel 31 APORT3XCH0 0x60 APORT3X Channel 0 APORT3YCH1 0x61 APORT3Y Channel 1 APORT3XCH2 0x62 APORT3X Channel 2 APORT3YCH3 0x63 APORT3Y Channel 3 APORT3XCH4 0x64 APORT3...

Page 706: ...0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 Access R R R Name APORTCONFLICT ACMPOUT ACMPACT Bit Name Reset Access Description 31 3 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 2 APORTCONFLICT 0 R APORT Conflict Output 1 if any of the APORT BUSes being requested by the ACMPn are also being requested by another p...

Page 707: ...nterrupt Flag Indicates that there has been a rising or falling edge on the analog comparator output 21 5 5 ACMPn_IFS Interrupt Flag Set Register Offset Bit Position 0x010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 Access W1 W1 W1 Name APORTCONFLICT WARMUP EDGE Bit Name Reset Access Description 31 3 Reserved To ensure compatibility with future...

Page 708: ...errupt flag Reading returns the value of the IF and clears the corresponding inter rupt flags This feature must be enabled globally in MSC 1 WARMUP 0 R W1 Clear WARMUP Interrupt Flag Write 1 to clear the WARMUP interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 0 EDGE 0 R W1 Clear EDGE Interrupt Flag Write 1 ...

Page 709: ...ved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 2 APORTCONFLICT 0 RW APORTCONFLICT Interrupt Enable Enable disable the APORTCONFLICT interrupt 1 WARMUP 0 RW WARMUP Interrupt Enable Enable disable the WARMUP interrupt 0 EDGE 0 RW EDGE Interrupt Enable Enable disable the EDGE interrupt EFM32JG1 Reference Manual ACMP Analog Comparator silabs...

Page 710: ...the APORT 6 APORT3XREQ 0 R 1 if the bus connected to APORT3X is requested Reports if the bus connected to APORT3X is being requested from the APORT 5 APORT2YREQ 0 R 1 if the bus connected to APORT2Y is requested Reports if the bus connected to APORT2Y is being requested from the APORT 4 APORT2XREQ 0 R 1 if the bus connected to APORT2X is requested Reports if the bus connected to APORT2X is being r...

Page 711: ... 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 0 0 Access R R R R R R R R R R Name APORT4YCONFLICT APORT4XCONFLICT APORT3YCONFLICT APORT3XCONFLICT APORT2YCONFLICT APORT2XCONFLICT APORT1YCONFLICT APORT1XCONFLICT APORT0YCONFLICT APORT0XCONFLICT EFM32JG1 Reference Manual ACMP Analog Comparator silabs com Smart Connected Energy friendly Preliminary Rev 0 6 710 ...

Page 712: ...flict with another pe ripheral Reports if the bus connected to APORT2Y is is also being requested by another peripheral 4 APORT2XCONFLICT 0 R 1 if the bus connected to APORT2X is in conflict with another pe ripheral Reports if the bus connected to APORT2X is is also being requested by another peripheral 3 APORT1YCONFLICT 0 R 1 if the bus connected to APORT1X is in conflict with another pe ripheral...

Page 713: ... 0 VADIV VA DIVVA 1 64 15 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 3 0 HYST 0x0 RW Hysteresis Select when ACMPOUT 0 Select hysteresis level when comparator output is 0 The hysteresis levels can vary please see the electrical characteristics for the device for more information Value Mode Description 0 HYST0 No hysteresis 1 HY...

Page 714: ... 1 VADIV VA DIVVA 1 64 15 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 3 0 HYST 0x0 RW Hysteresis Select when ACMPOUT 1 Select hysteresis level when comparator output is 1 The hysteresis levels can vary please see the electrical characteristics for the device for more information Value Mode Description 0 HYST0 No hysteresis 1 HY...

Page 715: ...0 Access RW Name OUTPEN Bit Name Reset Access Description 31 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 0 OUTPEN 0 RW ACMP Output Pin Enable Enable disable analog comparator output to pin EFM32JG1 Reference Manual ACMP Analog Comparator silabs com Smart Connected Energy friendly Preliminary Rev 0 6 714 ...

Page 716: ...fset Bit Position 0x044 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 Access RW Name OUTLOC EFM32JG1 Reference Manual ACMP Analog Comparator silabs com Smart Connected Energy friendly Preliminary Rev 0 6 715 ...

Page 717: ...ion 8 9 LOC9 Location 9 10 LOC10 Location 10 11 LOC11 Location 11 12 LOC12 Location 12 13 LOC13 Location 13 14 LOC14 Location 14 15 LOC15 Location 15 16 LOC16 Location 16 17 LOC17 Location 17 18 LOC18 Location 18 19 LOC19 Location 19 20 LOC20 Location 20 21 LOC21 Location 21 22 LOC22 Location 22 23 LOC23 Location 23 24 LOC24 Location 24 25 LOC25 Location 25 26 LOC26 Location 26 27 LOC27 Location 2...

Page 718: ...ogrammable sequence With the help of PRS and DMA the ADC can operate without CPU inter vention in EM2 and EM3 minimizing the number of powered up resources The ADC can further be du ty cycled to reduce the energy consumption 22 1 Introduction The ADC uses a Successive Approximation Register SAR architecture with a resolution of up to 12 bits at up to one million samples per second 1 Msps The integ...

Page 719: ...Programmable watermark DVL to generate SCAN interrupt Supports overflow and underflow interrupt generation Supports window compare function Conversion tailgating support for predictable periodic scans Programmable single channel conversion Triggered by software or PRS input Can be interleaved between two scan sequences One shot or repetitive mode Oversampling available Four deep FIFO to store conv...

Page 720: ... 3 Functional Description An overview of the ADC is shown in Figure 22 1 ADC Overview on page 719 APORT1X TEMP VSS VSS APORT2X Sequencer Control ADCn_SINGLEDATA ADCn_SCANDATA ADCn_SCANCTRLX ADCn_SINGLECTRL ADCn_SCANCTRL Prescaler ADC_CLK HFPERCLKADCn ADCn_SINGLECTRLX ADCn_STATUS ASYNCCLKADCn ADCCLKMODE Oversampling filter SINGLESAMPLE FIFO SCAN SAMPLE FIFO SCAN INPUTID ADCn_CMD ADCn_CTRL ADCn_CMPT...

Page 721: ...N and WARMMODE of the ADCn_CTRL register If the ASYNCCLKEN is set to ASNEEDED with WARMMODE set to NORMAL the ADC requests ASYNCCLK only when a conversion trigger is activated The ASYNCCLK request is withdrawn after the conversion is complete All other options keep the ASYNCCLK request ON until software programs these fields otherwise or changes the ADCCLKMODE to SYNC For EM2 or EM3 operation of t...

Page 722: ...s The CMPEN bit in the ADCn_SINGLECTRL register ena bles the window compare function and the latest converted data is compared against values programmed into the ADGT and ADLT fields of the ADCn_CMPTHR register and generates SINGLECMP interrupts if enabled The window compare function allows for com pare triggering both within if ADGT less than ADLT or out of if ADGT greater than ADLT window 22 3 3...

Page 723: ...wer option for sam pling rates between about 35 and 125 ksps It may also be useful for lower sampling rates where latency is important The reference selected for scan mode is kept warm but the ADC is powered down The ADC will initiate a 1 µs warmup period before a conversion begins Because the reference is kept warm the ADC will consume a small amount of standby current when it is not converting F...

Page 724: ... KEEPADCWARM Time a b c 1 µs ADC warmed up waiting for trigger Figure 22 4 ADC Analog Power Consumption With Different WARMUPMODE Settings Note When using any warm up mode other than NORMAL always switch back to the NORMAL mode before switching to another warm up mode EFM32JG1 Reference Manual ADC Analog to Digital Converter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 723 ...

Page 725: ...and odd num bered channels connect to the Y bus Unlike APORT1 through APORT4 APORT0 is not a shared resource It consists of a 16 channel X bus and a 16 channel Y bus each with dedicated I O pin connections Note that APORT0 is not available on all device families ch0 ch2 ch4 ch6 ch24 ch26 ch28 ch30 ch1 ch3 ch5 ch7 ch25 ch27 ch29 ch31 ch0 ch2 ch4 ch6 ch24 ch26 ch28 ch30 ch1 ch3 ch5 ch7 ch25 ch27 ch2...

Page 726: ...larity X Y X Y X Y X Y X Y Shared Bus n a BUSAX BUSAY BUSBX BUSBY BUSCX BUSCY BUSDX BUSDY CH31 PB15 PB15 CH30 PB14 PB14 CH29 PB13 PB13 CH28 PB12 PB12 CH27 PB11 PB11 CH26 CH25 CH24 CH23 PF7 PF7 CH22 PF6 PF6 CH21 PF5 PF5 CH20 PF4 PF4 CH19 PF3 PF3 CH18 PF2 PF2 CH17 PF1 PF1 CH16 PF0 PF0 CH15 CH14 CH13 PA5 PA5 CH12 PA4 PA4 CH11 PC11 PC11 PA3 PA3 CH10 PC10 PC10 PA2 PA2 CH9 PC9 PC9 PA1 PA1 CH8 PC8 PC8 PA...

Page 727: ... in both the POSSEL and NEGSEL fields it is possible to choose inputs from both X and Y buses even though X channels are physically connected to the positive mux INP_MUX and Y channels are physically connected to the negative mux INN_MUX For single ended operation DIFF 0 if the positive input is chosen from a Y channel the ADC performs a negative single ended conver sion and automatically inverts ...

Page 728: ...ended scan configuration In this example ADCn_SCANINPUTSEL has been configured to place APORT1CH16TO23 in the first third and fourth channel groups APORT4CH8TO15 has been placed in the second channel group ADCn_SCANMASK selects six of these channels for inclusion in the scan When an ADC scan is initiated with this configuration the ADC begins at SCANINPUTID0 and converts each enabled channel in tu...

Page 729: ... the negative input for SCANINPUT 9 11 13 and 15 may be re mapped to any of the even numbered channels in that group SCANIN PUT 8 10 12 or 14 Figure 22 8 ADC Differential Scan Mode Re mapping Negative Input Selections on page 728 shows the effects of the ADCn_SCAN NEGSEL register on the re mappable inputs The left side of the figure shows the default channel mapping and the right side of the figur...

Page 730: ...ut is from 0 to VFS For differential conversions the input to the converter is the difference between the positive and negative input selections This can range from VFS 2 to VFS 2 VFS for the converter is determined by a combination of the selected voltage reference VREF and programmable divider circuits on the ADC input and voltage reference paths Users have full control over the VREF and divider...

Page 731: ...iate choice where a differential reference of greater than 1 05 V is required VREFPN A differential version of VREFP with the reference source applied to the ADCn_EXTP and ADCn_EXTN pins and no at tenuation This is the appropriate choice where a differential reference of between 0 7 V and 1 05 V is required VBGRLOW An internal 0 78 V bandgap reference voltage The ADC reference voltage should be at...

Page 732: ...ial 3 0 V VREFATTFIX 0 VREFATT 2 ATTVREF 1 3 1 0 V VINATT 8 ATTVIN 2 3 3 0 V 1 5 V differential 3 0 V VREFATTFIX 0 VREFATT 2 ATTVREF 1 3 1 0 V VINATT 4 ATTVIN 1 3 6 0 V 3 0 V differential 3 6 V VREFATTFIX 1 VREFATT 0 ATTVREF 1 4 0 9 V VINATT 6 ATTVIN 1 2 3 6 V 1 8 V differential 22 3 7 Programming of Bias Current The ADC uses a chip level bias generator to provide bias current for its operation Th...

Page 733: ...o finish before acti vating see Figure 22 13 ADC Conversion Tailgating on page 732 The single channel will then follow immediately after the scan sequence In this way the scan sequence will always start immediately when triggered provided that the period between the scan trig gers is big enough to allow the single sample conversion that was triggered to finish before the next scan trigger arrives ...

Page 734: ... period AT If the ADC_CLK and the source of the trigger START command or PRS pulse are not synchronous the frequency of the input sam pling FS will experience a 11 2 to 21 2 ADC_CLK cycle jitter due to synchronization requirements To precisely control the sample frequency the PRSMODE can be set to TIMED mode In this mode a long PRS pulse is expected to trigger the ADC and its negative edge directl...

Page 735: ...ardless of when in the trigger occurs Software should not trigger conversions if PRS Timed mode is selected and PRSEN is set to 1 in the ADCn_SINGLECTRL ADCn_SCANCTRL register If the PRS Timed mode is being used the acquisition time AT must be set greater than 0 22 3 8 4 Output Results ADC output results are presented in 2 s complement form and the format for single ended and differential conversi...

Page 736: ...TRL With oversampling each input is sampled at 12 bits of resolution a number of times given by OVSRSEL and the results are filtered by a first order accumulate and dump filter to form the end result The data presented in the ADCn_SINGLEDATA and ADCn_SCANDATA registers are the direct contents of the accumulation register sum of samples However if the oversampling ratio is set higher than 16x the a...

Page 737: ...ts in order to get consistent results This means that if the ADC is warmed up with CHCON REFWARMIDLE set to 0 scan reference warmed up and the APORT switches for the first scan channel closed and a single trigger comes in the single conversion will have to wait 12 adc_clk_sar cycles before it can start even if single is using the same reference as scan In this case it might be more suitable to swi...

Page 738: ...EN in ADCn_SINGLECTRL ADCn_SCANCTRL is enabled ADC has two separate PRS outputs one for single channel and one for scan sequence A finished conversion results in a one ADC_CLK cycle pulse which is output to the Peripheral Reflex System PRS Note that the PRS pulse for scan is generated once after every channel conversion in the scan sequence 22 3 10 DMA Request The ADC has two DMA request lines SIN...

Page 739: ...ected ADC output The ADC has a 8LSB built in negative offset to allow for negative offset correction So with default offset value which corrects for the negative offset the converted ADCn_SINGLEDATA would match expected ADC output if there were no offset To get better noise immunity the sampling phase can be repeated with Over sampling enabled The result of the binary search is written to the SING...

Page 740: ...osen to come from ASYNCCLK ADCCLKMODE is set to ASYNC the ADC_CLK and the ADC peripheral clock are considered asynchronous and this adds some restrictions Due to a synchronization delay accessing the following registers takes extra time up to additional 7 HFPERCLK cycles ADCn_SINGLEDATA ADCn_SCANDATA ADCn_SINGLEDATAP ADCn_SCANDATAP ADCn_SCANDATAX ADCn_SCANDA TAXP ADCn_SINGLEFIFOCOUNT ADCn_SCANFIFO...

Page 741: ...e that no new triggers PRS are being issued It can take a few cycles from when a trigger is received to when SINGELACT SCANACT flags go high due to synchronization requirement If it is unclear when the triggers were issued and if those are under synchronization or not the user should add a small delay before checking the status flags If the SINGLEACT SCANACT status flags are high the corresponding...

Page 742: ...g Register 0x03C ADCn_IFS W1 Interrupt Flag Set Register 0x040 ADCn_IFC R W1 Interrupt Flag Clear Register 0x044 ADCn_IEN RW Interrupt Enable Register 0x048 ADCn_SINGLEDATA R a Single Conversion Result Data 0x04C ADCn_SCANDATA R a Scan Conversion Result Data 0x050 ADCn_SINGLEDATAP R Single Conversion Result Data Peek Register 0x054 ADCn_SCANDATAP R Scan Sequence Result Data Peek Register 0x068 ADC...

Page 743: ...5 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0x0 0x1F 0x00 0 0 0 0 0 0x0 Access RW RW RW RW RW RW RW RW RW RW Name CHCONMODE OVSRSEL TIMEBASE PRESC ADCCLKMODE ASYNCCLKEN TAILGATE SCANDMAWU SINGLEDMAWU WARMUPMODE EFM32JG1 Reference Manual ADC Analog to Digital Converter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 742 ...

Page 744: ...lt 6 X128 128 samples for each conversion result 7 X256 256 samples for each conversion result 8 X512 512 samples for each conversion result 9 X1024 1024 samples for each conversion result 10 X2048 2048 samples for each conversion result 11 X4096 4096 samples for each conversion result 23 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tio...

Page 745: ...TE 0 RW Conversion Tailgating Enable disable conversion tailgating Single channel conversions wait for a scan sequence to finish before starting Value Description 0 Scan sequence has priority but can be delayed by ongoing single channels 1 Scan sequence has priority and single channels will only start immedi ately after completion of a scan sequence 3 SCANDMAWU 0 RW SCANFIFO DMA Wakeup Selects whe...

Page 746: ... 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 Access W1 W1 W1 W1 Name SCANSTOP SCANSTART SINGLESTOP SINGLESTART Bit Name Reset Access Description 31 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 3 SCANSTOP 0 W1 Scan Sequence Stop Write a 1 to stop scan sequence 2 SCANSTART 0 W1 Scan Sequ...

Page 747: ... tions 12 WARM 0 R ADC Warmed Up ADC is warmed up 11 10 PROGERR 0x0 R Programming Error Status Programming Error Status Mode Value Description BUSCONF x1 APORT reported a BUS Conflict NEGSELCONF 1x SINGLECTRL s NEGSEL choice is invalid with respect to POSSEL choice Occurs when two X channels or two Y channels are selected 9 SCANREFWARM 0 R Scan Reference Warmed Up Reference selected for scan mode ...

Page 748: ... 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0x0 0xFF 0xFF 0x0 0x0 0 0 0 Access RW RW RW RW RW RW RW RW RW RW Name CMPEN PRSEN AT NEGSEL POSSEL REF RES ADJ DIFF REP EFM32JG1 Reference Manual ADC Analog to Digital Converter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 747 ...

Page 749: ...ock cycles acquisition time for single channel 4 8CYCLES 8 conversion clock cycles acquisition time for single channel 5 16CYCLES 16 conversion clock cycles acquisition time for single channel 6 32CYCLES 32 conversion clock cycles acquisition time for single channel 7 64CYCLES 64 conversion clock cycles acquisition time for single channel 8 128CYCLES 128 conversion clock cycles acquisition time fo...

Page 750: ...put to the ADC for single channel operation Software can choose any of the 32 channels of any BUS as positive input In DIFF mode POSSEL and NEGSEL need to be chosen from different resources X or Y If an X BUS is connected to POSSEL only a Y BUS can connect to NEGSEL and vice versa The user can also select some internal nodes as positive input for single ended sampling These internal nodes cannot b...

Page 751: ... is available TEMP 243 Temperature sensor DAC0OUT0 244 DAC0 output 0 Not Applicable if no DAC is available TESTP 245 Reserved for future expansion SP1 246 Reserved for future expansion SP2 247 Reserved for future expansion DAC0OUT1 248 DAC0 output 1 Not Applicable if no DAC is available SUBLSB 249 SUBLSB measurement enabled OPA3 250 OPA3 output Not Applicable if no OPA is available VSS 255 VSS 7 5...

Page 752: ...nel Result Adjustment Select single channel result adjustment Value Mode Description 0 RIGHT Results are right adjusted 1 LEFT Results are left adjusted 1 DIFF 0 RW Single Channel Differential Mode Select single ended or differential input Value Description 0 Single ended input 1 Differential input 0 REP 0 RW Single Channel Repetitive Mode Enable disable repetitive single channel conversions Value...

Page 753: ...6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0x0 0x0 0 0 0x0 0x0 0x0 0 0x0 Access RW RW RW RW RW RW RW RW RW RW Name CONVSTARTDELAYEN CONVSTARTDELAY PRSSEL PRSMODE FIFOOFACT DVL VINATT VREFATT VREFATTFIX VREFSEL EFM32JG1 Reference Manual ADC Analog to Digital Converter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 752 ...

Page 754: ...PRS trigger for single channel Value Mode Description 0 PRSCH0 PRS ch 0 triggers single channel 1 PRSCH1 PRS ch 1 triggers single channel 2 PRSCH2 PRS ch 2 triggers single channel 3 PRSCH3 PRS ch 3 triggers single channel 4 PRSCH4 PRS ch 4 triggers single channel 5 PRSCH5 PRS ch 5 triggers single channel 6 PRSCH6 PRS ch 6 triggers single channel 7 PRSCH7 PRS ch 7 triggers single channel 8 PRSCH8 P...

Page 755: ... for VREF attenuation factor when VREFSEL is 1 2 or 5 Used to set VREF attenuation factor 3 VREFATTFIX 0 RW Enable fixed scaling on VREF Enables fixed scaling on VREF Value Description 0 VREFATT setting is used to scale VREF when VREFSEL is 1 2 or 5 1 A fixed VREF attenuation is used to cover a large reference source range When VREFATT 0 the scaling factor is 1 4 For non zero val ues of VREFATT th...

Page 756: ... 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0x0 0x0 0x0 0 0 0 Access RW RW RW RW RW RW RW RW Name CMPEN PRSEN AT REF RES ADJ DIFF REP EFM32JG1 Reference Manual ADC Analog to Digital Converter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 755 ...

Page 757: ...on clock cycles acquisition time for scan 3 4CYCLES 4 conversion clock cycles acquisition time for scan 4 8CYCLES 8 conversion clock cycles acquisition time for scan 5 16CYCLES 16 conversion clock cycles acquisition time for scan 6 32CYCLES 32 conversion clock cycles acquisition time for scan 7 64CYCLES 64 conversion clock cycles acquisition time for scan 8 128CYCLES 128 conversion clock cycles ac...

Page 758: ...ence Result Adjustment Select scan sequence result adjustment Value Mode Description 0 RIGHT Results are right adjusted 1 LEFT Results are left adjusted 1 DIFF 0 RW Scan Sequence Differential Mode Select single ended or differential input Value Description 0 Single ended input 1 Differential input 0 REP 0 RW Scan Sequence Repetitive Mode Enable disable repetitive scan sequence Value Description 0 ...

Page 759: ...4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0x0 0x0 0 0 0x0 0x0 0x0 0 0x0 Access RW RW RW RW RW RW RW RW RW RW Name CONVSTARTDELAYEN CONVSTARTDELAY PRSSEL PRSMODE FIFOOFACT DVL VINATT VREFATT VREFATTFIX VREFSEL EFM32JG1 Reference Manual ADC Analog to Digital Converter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 758 ...

Page 760: ...Select Select PRS trigger for scan sequence Value Mode Description 0 PRSCH0 PRS ch 0 triggers scan sequence 1 PRSCH1 PRS ch 1 triggers scan sequence 2 PRSCH2 PRS ch 2 triggers scan sequence 3 PRSCH3 PRS ch 3 triggers scan sequence 4 PRSCH4 PRS ch 4 triggers scan sequence 5 PRSCH5 PRS ch 5 triggers scan sequence 6 PRSCH6 PRS ch 6 triggers scan sequence 7 PRSCH7 PRS ch 7 triggers scan sequence 8 PRS...

Page 761: ...e for VREF attenuation factor when VREFSEL is 1 2 or 5 Used to set VREF attenuation factor 3 VREFATTFIX 0 RW Enable fixed scaling on VREF Enables fixed scaling on VREF Value Description 0 VREFATT setting is used to scale VREF when VREFSEL is 1 2 or 5 1 A fixed VREF attenuation is used to cover a large reference source range When VREFATT 0 the scaling factor is 1 4 For non zero val ues of VREFATT t...

Page 762: ...osition 0x020 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access RW Name SCANINPUTEN EFM32JG1 Reference Manual ADC Analog to Digital Converter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 761 ...

Page 763: ...xxx1xxxxxx ADCn_INPUT6 included in mask INPUT7 xxxxxxxxxxxxxxxxxxxxx xxx1xxxxxxx ADCn_INPUT7 included in mask INPUT31 1xxxxxxxxxxxxxxxxxxxx xxxxxxxxxx ADCn_INPUT31 included in mask DIFF 1 INPUT0INPUT0NEG SEL xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxx1 Positive input ADCn_INPUT0 Negative input chosen by IN PUT0NEGSEL included in mask INPUT1INPUT2 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxx1x Positive input ADCn_INPUT1 N...

Page 764: ...sitive input ADCn_INPUT14 Negative input ADCn_INPUT15 in cluded in mask INPUT15IN PUT15NEGSEL xxxxxxxxxxxxxxxx1xxxx xxxxxxxxxxx Positive input ADCn_INPUT15 Negative input chosen by IN PUT15NEGSEL included in mask INPUT16INPUT17 xxxxxxxxxxxxxxx1xxxxx xxxxxxxxxxx Positive input ADCn_INPUT16 Negative input ADCn_INPUT17 in cluded in mask INPUT28INPUT29 xxx1xxxxxxxxxxxxxxxxx xxxxxxxxxxx Positive input ...

Page 765: ...7 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 0x00 0x00 0x00 Access RW RW RW RW Name INPUT24TO31SEL INPUT16TO23SEL INPUT8TO15SEL INPUT0TO7SEL EFM32JG1 Reference Manual ADC Analog to Digital Converter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 764 ...

Page 766: ...1 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 20 16 INPUT16TO23SEL 0x00 RW Inputs chosen for ADCn_INPUT16 ADCn_INPUT23 as referred in SCANMASK Mode Value Description APORT0CH0TO7 0 Select APORT0 s CH0 CH7 as ADCn_INPUT16 ADCn_INPUT23 APORT0CH8TO15 1 Select APORT0 s CH8 CH15 as ADCn_INPUT16 ADCn_INPUT23 APORT1CH0TO7 4 Select APORT...

Page 767: ...15 7 5 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 4 0 INPUT0TO7SEL 0x00 RW Inputs chosen for ADCn_INPUT7 ADCn_INPUT0 as referred in SCANMASK Mode Value Description APORT0CH0TO7 0 Select APORT0 s CH0 CH7 as ADCn_INPUT0 ADCn_INPUT7 APORT0CH8TO15 1 Select APORT0 s CH8 CH15 as ADCn_INPUT0 ADCn_INPUT7 APORT1CH0TO7 4 Select APORT1 s C...

Page 768: ... 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 0x3 0x2 0x1 0x3 0x2 0x1 0x0 Access RW RW RW RW RW RW RW RW Name INPUT15NEGSEL INPUT13NEGSEL INPUT11NEGSEL INPUT9NEGSEL INPUT6NEGSEL INPUT4NEGSEL INPUT2NEGSEL INPUT0NEGSEL EFM32JG1 Reference Manual ADC Analog to Digital Converter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 767 ...

Page 769: ... INPUT14 Selects ADCn_INPUT14 as negative channel input 11 10 INPUT11NEGSEL 0x2 RW Negative Input select Register for ADCn_INPUT11 in Differential Scan mode Selects negative channel Value Mode Description 0 INPUT8 Selects ADCn_INPUT8 as negative channel input 1 INPUT10 Selects ADCn_INPUT10 as negative channel input 2 INPUT12 Selects ADCn_INPUT12 as negative channel input 3 INPUT14 Selects ADCn_INP...

Page 770: ...NPUT2NEGSEL 0x1 RW Negative Input select Register for ADCn_INPUT2 in Differential Scan mode Selects negative channel Value Mode Description 0 INPUT1 Selects ADCn_INPUT1 as negative channel input 1 INPUT3 Selects ADCn_INPUT3 as negative channel input 2 INPUT5 Selects ADCn_INPUT5 as negative channel input 3 INPUT7 Selects ADCn_INPUT7 as negative channel input 1 0 INPUT0NEGSEL 0x0 RW Negative Input s...

Page 771: ...ption 31 16 ADGT 0x0000 RW Greater Than Compare Threshold Compare threshold value for greater than comparison Must match the conversion data representation chosen 15 0 ADLT 0x0000 RW Less Than Compare Threshold Compare threshold value for less than comparison Must match the conversion data representation chosen EFM32JG1 Reference Manual ADC Analog to Digital Converter silabs com Smart Connected En...

Page 772: ...re compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 12 VFAULTCLR 0 RW Clear VREFOF flag Use this bit to request clearing of the VREFOF flag If VREFOF irq is enabled and is triggered the user must set this bit in the ISR to clear VREFOF The user needs to reset this bit to enable VREFOF to trigger further IRQs upon VREF overflow conditions 11 4 Reserved T...

Page 773: ...3 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0x40 0x7 0x8 0 0x40 0x7 0x8 Access RW RW RW RW RW RW RW RW Name CALEN SCANGAIN SCANOFFSETINV SCANOFFSET OFFSETINVMODE SINGLEGAIN SINGLEOFFSETINV SINGLEOFFSET EFM32JG1 Reference Manual ADC Analog to Digital Converter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 772 ...

Page 774: ...VMODE 0 RW Negative single ended offset calibration is enabled When enabled along with CALEN bit the ADC performs negative singled ended conversion When not enabled if CALEN is set DIFF bit of SINGLECTRL register decides whether to do positive single ended or differential conversion 14 8 SINGLEGAIN 0x40 RW Single Mode Gain Calibration Value This register contains the gain calibration value used wi...

Page 775: ...18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 0 0 Access R R R R R R R R R R Name PROGERR VREFOV SCANCMP SINGLECMP SCANUF SINGLEUF SCANOF SINGLEOF SCAN SINGLE EFM32JG1 Reference Manual ADC Analog to Digital Converter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 774 ...

Page 776: ...ions 11 SCANUF 0 R Scan FIFO Underflow Interrupt Flag Indicates scan result FIFO underflow when this bit is set An underflow occurs if the FIFO is read and there is no data avail able 10 SINGLEUF 0 R Single FIFO Underflow Interrupt Flag Indicates single result FIFO underflow when this bit is set An underflow occurs if the FIFO is read and there is no data available 9 SCANOF 0 R Scan FIFO Overflow ...

Page 777: ...on in 1 2 Conven tions 17 SCANCMP 0 W1 Set SCANCMP Interrupt Flag Write 1 to set the SCANCMP interrupt flag 16 SINGLECMP 0 W1 Set SINGLECMP Interrupt Flag Write 1 to set the SINGLECMP interrupt flag 15 12 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 11 SCANUF 0 W1 Set SCANUF Interrupt Flag Write 1 to set the SCANUF interrupt flag ...

Page 778: ...R W1 Clear SINGLECMP Interrupt Flag Write 1 to clear the SINGLECMP interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 15 12 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 11 SCANUF 0 R W1 Clear SCANUF Interrupt Flag Write 1 to clear the SCANUF ...

Page 779: ...Interrupt Enable Enable disable the SCANCMP interrupt 16 SINGLECMP 0 RW SINGLECMP Interrupt Enable Enable disable the SINGLECMP interrupt 15 12 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 11 SCANUF 0 RW SCANUF Interrupt Enable Enable disable the SCANUF interrupt 10 SINGLEUF 0 RW SINGLEUF Interrupt Enable Enable disable the SINGLE...

Page 780: ... this field pops one entry from the SINGLE FIFO 22 5 19 ADCn_SCANDATA Scan Conversion Result Data Actionable Reads Offset Bit Position 0x04C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access R Name DATA Bit Name Reset Access Description 31 0 DATA 0x00000000 R Scan Conversion Result Data The register holds the results from the last scan mo...

Page 781: ...field will not pop an entry from the SINGLE FIFO 22 5 21 ADCn_SCANDATAP Scan Sequence Result Data Peek Register Offset Bit Position 0x054 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access R Name DATAP Bit Name Reset Access Description 31 0 DATAP 0x00000000 R Scan Conversion Result Data Peek The register holds the results from the last sca...

Page 782: ...the SCAN FIFO 22 5 23 ADCn_SCANDATAXP Scan Sequence Result Data Data Source Peek Register Offset Bit Position 0x06C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 0x0000 Access R R Name SCANINPUTIDPEEK DATAP Bit Name Reset Access Description 31 21 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Co...

Page 783: ...PORT 6 APORT3XREQ 0 R 1 if the bus connected to APORT3X is requested Reports if the bus connected to APORT3X is being requested from the APORT 5 APORT2YREQ 0 R 1 if the bus connected to APORT2Y is requested Reports if the bus connected to APORT2Y is being requested from the APORT 4 APORT2XREQ 0 R 1 if the bus connected to APORT2X is requested Reports if the bus connected to APORT2X is being reques...

Page 784: ... 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 0 0 Access R R R R R R R R R R Name APORT4YCONFLICT APORT4XCONFLICT APORT3YCONFLICT APORT3XCONFLICT APORT2YCONFLICT APORT2XCONFLICT APORT1YCONFLICT APORT1XCONFLICT APORT0YCONFLICT APORT0XCONFLICT EFM32JG1 Reference Manual ADC Analog to Digital Converter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 783 ...

Page 785: ... with another pe ripheral Reports if the bus connected to APORT2Y is is also being requested by another peripheral 4 APORT2XCONFLICT 0 R 1 if the bus connected to APORT2X is in conflict with another pe ripheral Reports if the bus connected to APORT2X is is also being requested by another peripheral 3 APORT1YCONFLICT 0 R 1 if the bus connected to APORT1Y is in conflict with another pe ripheral Repo...

Page 786: ...mber of unread data available in Single FIFO 22 5 27 ADCn_SCANFIFOCOUNT Scan FIFO Count Register Offset Bit Position 0x088 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 Access R Name SCANDC Bit Name Reset Access Description 31 3 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 2 0 SCAN...

Page 787: ...ntent Write a 1 to clear Single FIFO content 22 5 29 ADCn_SCANFIFOCLEAR Scan FIFO Clear Register Offset Bit Position 0x090 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 Access W1 Name SCANFIFOCLEAR Bit Name Reset Access Description 31 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 0 ...

Page 788: ...12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 Access RW RW RW RW RW RW RW RW Name APORT4YMASTERDIS APORT4XMASTERDIS APORT3YMASTERDIS APORT3XMASTERDIS APORT2YMASTERDIS APORT2XMASTERDIS APORT1YMASTERDIS APORT1XMASTERDIS EFM32JG1 Reference Manual ADC Analog to Digital Converter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 787 ...

Page 789: ... if selected by POSSEL or NEGSEL or SCANINPUTSEL When 1 ADC only passively monitors the APORT bus and the selection of the channel for the selected bus is ignored The channel selection is done by the device that masters the APORT bus This bit allows multiple APORT connected devices to monitor the same APORT bus simultaneously Value Description 0 APORT mastering enabled 1 APORT mastering disabled 6...

Page 790: ... the channel for the selected bus is ignored The channel selection is done by the device that masters the APORT bus This bit allows multiple APORT connected devices to monitor the same APORT bus simultaneously Value Description 0 APORT mastering enabled 1 APORT mastering disabled 2 APORT1XMASTER DIS 0 RW APORT1X Master Disable Determines if the ADC will request this APORT bus if selected by POSSEL...

Page 791: ...oduction The current digital to analog converter IDAC can source or sink a configurable constant current from a pin or the ADC The current is configurable with several ranges of various step sizes 23 2 Features Can source and sink current Programmable constant output current Selectable current range between 0 05 µA and 64 µA Each range is linearly programmable in 32 steps Support for current calib...

Page 792: ...L_MINOUTTRANS IDAC_CTRL_APORT IDAC_APORT_STATUS Figure 23 1 IDAC Overview 23 3 1 Current Programming The four different current ranges can be selected by configuring the RANGESEL bitfield in IDAC_CURRPROG The current output in each range is linearly programmable in 32 steps and is controlled by the STEPSEL bitfield in IDAC_CURRPROG These current rang es and their step sizes are shown in Table 23 1...

Page 793: ...t Modes The IDAC can output current to a pin through the APORT bus system The IDAC is connected to APORT bus 1x and 1y channel 0 31 The IDAC output is enabled by first configuring APORTOUTSEL in IDAC_CTRL to the desired APORT channel and then setting APOR TOUTEN in IDAC_CTRL For details regarding setting up the APORT see 23 3 5 APORT Configuration EFM32JG1 Reference Manual IDAC Current Digital to ...

Page 794: ... the APORT channel by clearing APORTOUTEN in IDAC_CTRL The mapping for IDAC0 outputs to external I O connections is shown in Table 23 2 IDAC0 Bus and Pin Mapping on page 793 Note that this table shows the mapping for an entire family of devices Enumerations for the APORTOUTSEL field can be determmined by finding the desired pin connection in the table and then combining the IDAC Port polarity and ...

Page 795: ... IDAC can be duty cycled meaning that it can source current at very low overhead current consumption at the cost of response time and accuracy By default duty cycling is enabled in EM2 and EM3 and disabled in EM0 and EM1 Setting EM2DUTYCYCLEDIS in IDAC_DUTYCONFIG will disable duty cycling in EM2 and EM3 Note that sinking current can not be done with duty cycled references so measures needs to be t...

Page 796: ... by configuring for example a CC channel to com pare match with PRSLEVEL selected I T OFF ON T PRS input Figure 23 2 IDAC Charge Injection Example 23 4 Register Map The offset register address is relative to the registers base address Offset Name Type Description 0x000 IDAC_CTRL RW Control Register 0x004 IDAC_CURPROG RW Current Programming Register 0x00C IDAC_DUTYCONFIG RW Duty Cycle Configauratio...

Page 797: ...14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 0 0 0 0 0x00 0 0 0 0 Access RW RW RW RW RW RW RW RW RW RW Name PRSSEL APORTOUTENPRS APORTMASTERDIS EM2DELAY PWRSEL APORTOUTSEL APORTOUTEN MINOUTTRANS CURSINK EN EFM32JG1 Reference Manual IDAC Current Digital to Analog Converter silabs com Smart Connected Energy friendly Preliminary Rev 0 6 796 ...

Page 798: ...Description 0 APORT output enable controlled by IDAC_APORTOUTEN 1 APORT output enable controlled by PRS channel selected by PRSSEL 15 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 14 APORTMASTERDIS 0 RW APORT Bus Master Disable Determines if the IDAC will request the APORT bus selected by OUTMODE This bit allows multiple APORT conn...

Page 799: ... APORT1XCH30 0x3e APORT1X Channel 30 APORT1YCH31 0x3f APORT1Y Channel 31 3 APORTOUTEN 0 RW APORT Output Enable Set to enable the IDAC output to APORT if APORTOUTENPRS is not set 2 MINOUTTRANS 0 RW Minimum Output Transition Enable Set to enable minimum output transition mode for the IDAC 1 CURSINK 0 RW Current Sink Enable Set to enable the IDAC as a current sink By default the IDAC sources current ...

Page 800: ... write bits to 0 More information in 1 2 Conven tions 12 8 STEPSEL 0x00 RW Current Step Size Select Select the step within each range The size of each step depends on the RANGESEL setting RANGESEL settings of 0 1 2 and 3 correspond to step sizes of 50 nA 100 nA 500 nA and 2000 nA respectively See step details 7 2 Reserved To ensure compatibility with future devices always write bits to 0 More info...

Page 801: ...Conven tions 23 5 4 IDAC_STATUS Status Register Offset Bit Position 0x018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 Access R Name APORTCONFLICT Bit Name Reset Access Description 31 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 1 APORTCONFLICT 0 R APORT Conflict Output 1 if any o...

Page 802: ...s always write bits to 0 More information in 1 2 Conven tions 23 5 6 IDAC_IFS Interrupt Flag Set Register Offset Bit Position 0x024 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 Access W1 W1 Name APORTCONFLICT CURSTABLE Bit Name Reset Access Description 31 2 Reserved To ensure compatibility with future devices always write bits to 0 More informatio...

Page 803: ... Flag Write 1 to clear the CURSTABLE interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 23 5 8 IDAC_IEN Interrupt Enable Register Offset Bit Position 0x02C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 Access RW RW Name APORTCONFLICT CURSTABLE Bit Name Reset A...

Page 804: ...NFLICT APORT Request Status Register Offset Bit Position 0x038 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 Access R R Name APORT1YCONFLICT APORT1XCONFLICT Bit Name Reset Access Description 31 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 3 APORT1YCONFLICT 0 R 1 if the bus connec...

Page 805: ... that implements a Cyclic Redundancy Check CRC function It supports both 32 bit and 16 bit polynomials The supported 32 bit polynomial is 0x04C11DB7 IEEE 802 3 while the 16 bit polynomial can be programmed to any value depending on the needs of the application Common 16 bit polynomials are 0x1021 CCITT 16 0x3D65 IEC16 MBus and 0x8005 ZigBee 802 15 4 and USB 24 2 Features Programmable 16 bit polyno...

Page 806: ...A byte reorder byte level bit reversal Hardware CRC Calculation Unit Seed word or byte bit reversal POLY 0x04C11DB7 16 bit Programmable 32 bit Fixed Polynomial Selection DATA Figure 24 1 GPCRC Overview EFM32JG1 Reference Manual GPCRC General Purpose Cyclic Redundancy Check silabs com Smart Connected Energy friendly Preliminary Rev 0 6 805 ...

Page 807: ...RC_INPUTDATABYTE register via the APB bus based on different data size If BYTEMODE in GPCRC_CTRL is set only the least significant byte of the data word will be used for the CRC calculation no matter which input register is written There are also three output registers for different ordering Reading from GPCRC_DATA will get the result based on the polynomial in reversed order while reading from GP...

Page 808: ...bit 6 bit 2 bit 0 bit 3 bit 1 Byte 1 bit 7 bit 5 bit 4 bit 6 bit 2 bit 0 bit 3 bit 1 Byte 2 bit 7 bit 5 bit 4 bit 6 bit 2 bit 0 bit 3 bit 1 Byte 3 bit 7 bit 5 bit 4 bit 6 bit 2 bit 0 bit 3 bit 1 Byte 3 bit 0 bit 2 bit 3 bit 1 bit 5 bit 7 bit 4 bit 6 Byte 2 bit 0 bit 2 bit 3 bit 1 bit 5 bit 7 bit 4 bit 6 Byte 0 bit 0 bit 2 bit 3 bit 1 bit 5 bit 7 bit 4 bit 6 Byte 1 bit 0 bit 2 bit 3 bit 1 bit 5 bit...

Page 809: ... Data Ordering Example 16 bit MSB first to LSB first Assuming a word input byte order of B3 B2 B1 B0 the values used in the CRC calculation for the various settings of the byte level bit reversal and byte reordering are shown in Table 24 1 Byte Level Bit Reversal and Byte Reordering Results B3 B2 B1 B0 Input Order on page 808 Table 24 1 Byte Level Bit Reversal and Byte Reordering Results B3 B2 B1 ...

Page 810: ...Description 0x000 GPCRC_CTRL RW Control Register 0x004 GPCRC_CMD W1 Command Register 0x008 GPCRC_INIT RWH CRC Init Value 0x00C GPCRC_POLY RW CRC Polynomial Value 0x010 GPCRC_INPUTDATA W Input 32 bit Data Register 0x014 GPCRC_INPUTDATAHWORD W Input 16 bit Data Register 0x018 GPCRC_INPUTDATABYTE W Input 8 bit Data Register 0x01C GPCRC_DATA R CRC Data Register 0x020 GPCRC_DATAREV R CRC Data Reverse R...

Page 811: ...25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 Access RW RW RW RW RW RW Name AUTOINIT BYTEREVERSE BITREVERSE BYTEMODE POLYSEL EN EFM32JG1 Reference Manual GPCRC General Purpose Cyclic Redundancy Check silabs com Smart Connected Energy friendly Preliminary Rev 0 6 810 ...

Page 812: ...n each byte 8 BYTEMODE 0 RW Byte Mode Enable Treats all writes as bytes Only the least significant byte of the data word will be uesd for CRC calculation for all writes 7 5 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 4 POLYSEL 0 RW Polynomial Select Selects 16 bit CRC programmable polynomial or 32 bit CRC fixed polynomial Value M...

Page 813: ...ng 1 to this bit initialize the CRC by writing the INIT value in CRC_INIT to CRC_DATA 24 5 3 GPCRC_INIT CRC Init Value Offset Bit Position 0x008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access RWH Name INIT Bit Name Reset Access Description 31 0 INIT 0x00000000 RWH CRC Initialization Value This value is loaded into CRC_DATA upon issuing...

Page 814: ...he lowest degree term is in the highest bit position of POLY Additionally the highest degree term in the polynomial is implicit Further examples of the CRC confiuguration can be found in the documen tation 24 5 5 GPCRC_INPUTDATA Input 32 bit Data Register Offset Bit Position 0x010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access W Name I...

Page 815: ...r is written the CRC value is updated 24 5 7 GPCRC_INPUTDATABYTE Input 8 bit Data Register Offset Bit Position 0x018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 Access W Name INPUTDATABYTE Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 7 0 IN...

Page 816: ...mmand 24 5 9 GPCRC_DATAREV CRC Data Reverse Register Offset Bit Position 0x020 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access R Name DATAREV Bit Name Reset Access Description 31 0 DATAREV 0x00000000 R Data Reverse Value Bit reversed version of CRC Data register When a 32 bit CRC polynomial is selected the reversal occurs on the entire ...

Page 817: ...e Reset Access Description 31 0 DATABYTEREV 0x00000000 R Data Byte Reverse Value Byte reversed version of CRC Data register When a 32 bit CRC polynomial is selected the bytes are swizzled to B0 B1 B2 B3 When a 16 bit CRC polynomial is selected the bytes are swizzled to B2 B3 B1 B0 EFM32JG1 Reference Manual GPCRC General Purpose Cyclic Redundancy Check silabs com Smart Connected Energy friendly Pre...

Page 818: ...ryptography ECC SHA 1 SHA 224 SHA 256 and various block cipher modes based on the Advanced Encryption Standard also known as AES FIPS 197 CRYPTO is capable of autonomously fetching data performing cipher operations and storing data across multiple blocks When the source data is not a multiple of 16 bytes 128 bits Zero padding can be included in the last block Block operations such as Counter Mode ...

Page 819: ... request signals for data read and write Optional XOR Data write Interrupt on finished operations Extensive software support Extensive software library in Simplicity Studio Implements all major cryptographic algorithms AES SHA 1 SHA 2 and ECC Implements legacy algorithms DES 3DES MD4 MD5 and RC4 Hardware accelerated when possible 25 3 Usage and Programming Interface Many security systems fail due ...

Page 820: ...equencer DATA1 127 0 DATA0 127 0 DATA3 127 0 DATA2 127 0 KEYBUF 255 0 KEY 255 0 DDATA0 255 0 AHB bus Control DDATA4 255 0 DDATA1 255 0 DDATA0 255 0 DDATA2 255 0 DDATA3 255 0 QDATA0 511 0 QDATA1 511 0 Figure 25 1 CRYPTO Overview EFM32JG1 Reference Manual CRYPTO Crypto Accelerator silabs com Smart Connected Energy friendly Preliminary Rev 0 6 819 ...

Page 821: ...s is used in a large variety of block cipher modes All of these registers operate on DATA0 DATA1 can be accessed through CRYPTO_DATA1 32 bit and CRYPTO_DATA1BYTE 8 bit The remaining data registers have regular 32 bit access through their respective registers Note that all data registers require a full read or write to be fully accessed This means that the 128 bit registers need four 32 bit reads w...

Page 822: ...e data CRYPTO_DDATA2 DATA1 Read data DDATA2 256 bit DATA0 CRYPTO_DDATA3 DATA3 Read data DDATA3 256 bit DATA2 Write data Write data CRYPTO_DDATA1 KEY Read data DDATA1 256 bit Write data CRYPTO_DDATA4 KEYBUF Read data DDATA4 256 bit Write data CRYPTO_QDATA0 DDATA1 Read data QDATA0 512 bit DDATA0 CRYPTO_QDATA1 DDATA3 Read data QDATA1 512 bit DDATA2 Write data Figure 25 2 CRYPTO Data and Key Register ...

Page 823: ...le implements a set of instructions in order to load and manipulate data effectively These instructions are grouped into four types ALU instructions arithmetic and logical bitwise operations Transfer instructions moving data between registers and external peripherals like DMA Conditional instructions conditionally execute instructions based on context Special instructions various crypto and suppor...

Page 824: ...ATA0 V0 V1 carry 128 If V0 DDATA0 then V1 DDATA0If re sultwidth is 128b then carry is undefined MADD DDATA0 V0 V1 mod P If V0 DDATA0 then V1 DDATA0 MADD32 DDATA0 i V0 i V1 i Word wise addition carry is not modifiedIf V0 DDATA0 then V1 DDATA0 SUB DDATA0 V0 V1 V1 DDATA0If V1 is 128b and resultwidth 128b then upper 128b are unknown SUBC DDATA0 V0 V1 carry V1 DDATA0If V1 is 128b and resultwidth 128b t...

Page 825: ... DATAX DATA1 DDATA1 QDATA1 QDA TA1BIG DATAxTODATAy DATAy DATAx DATAxTODATA0XOR DATA0 DATA0 DATAx If resultwidth is 128b then carry is unde fined DATAxTODATA0XORLEN DATA0 DATA0 DATAx 2 LENGTH 1 LENGTH is LENGTHA or LENGTHB de pending on active part of sequenceIf result width is 128b then carry is undefined DDATAxTODDATAy DDATAy DDATAx DDATAxHTODATA1 DATA1 DDATAx 255 128 Bits DDATA2 259 256 become u...

Page 826: ...1INCCLR instructions 25 4 2 3 MULx details For the MULx instructions not MMUL MULWIDTH in CRYPTO_WAC specifies the width of operands DDATA1 and sometimes V1 This is useful in order to optimize performance because multiplications take the same number of cycles as the bits in the operands plus a couple of cycles for setup As for the other ALU instructions RESULTWIDTH limits the width of the final re...

Page 827: ...he number of bytes in the set and BLOCKSIZE to the size of the blocks in the set The sequence will then be repeated N times where N is LENGTHA BLOCKSIZE if LENGTHA is a multiple of BLOCKSIZE or ceiling LENGTHA BLOCKSIZE if not In the latter case data written by DMA will be zero padded up to BLOCKSIZE if it is written to a register which has a size equal to BLOCKSIZE One notable exception is when L...

Page 828: ...erKey This key must be loaded into the KEY regis ters prior to the decryption After one decryption the resulting key will be the PlainKey The resulting PlainKey CipherKey is only de pendent on the value in the KEY registers before encryption decryption The resulting keys and data are shown in Figure 25 4 CRYPTO Key and Data Definitions on page 827 PlainText CipherText PlainKey CipherKey Encryption...

Page 829: ... S1 0 S1 1 S2 0 S2 1 S0 2 S0 3 S1 2 S1 3 S2 2 S2 3 S3 2 S3 3 S3 0 S3 1 KEY0 KEY1 KEY2 KEY3 a16 a20 a17 a21 a18 a22 a24 a28 a25 a29 a26 a30 a27 a31 a19 a23 Figure 25 5 CRYPTO Data and Key Orientation as Defined in the Advanced Encryption Standard EFM32JG1 Reference Manual CRYPTO Crypto Accelerator silabs com Smart Connected Energy friendly Preliminary Rev 0 6 828 ...

Page 830: ...3D2E1F0 0xFFC00B31 0x510E527F 0x00000000 0x68581511 0x9B05688C 0x00000000 0x64F98FA7 0x1F83D9AB 0x00000000 0xBEFA4FA4 0x5BE0CD19 Table 25 6 SHA Preparations STEP ACTION Description STEP0 DDATA1TODDATA0 Copy init data to DDATA0 STEP1 SELDDATA0DDATA1 Select DDATA0 and DDATA1 as operands for SHA instruction Then for each 512 bit block write the block to CRYPTO_QDATA1BIG execute the instructions liste...

Page 831: ...YPTO_DATA1 CRYPTO_DDATA1 CRYP TO_QDATA1 or CRYPTO_QDATA1BIG read depending on DMA1MODE in CRYPTO_CTRL Note DMAxRSEL in CRYPTO_CTRL has to be set to the data registers that are to be read using the respective DMA channels on a DATATODMAx instruction As an important note DMAxRSEL in CRYPTO_CTRL selects what is read from any of the selectable read registers during an ongoing DATATODMAx transfer verif...

Page 832: ...in CRYPTO when reading data out from the CRYPTO module e g CRYPTO_DATA0UAR CRYPTO_DATA1UAR CRYPTO_DDATA0UAR CRYPTO_DDATA1UAR CRYPTO_QDATA0UAR etc When an unaligned buffer is written to a CRYPTO buffer CRYPTO stores the N first bytes and the 4 N last bytes internally When read ing out from an UAR register these bytes are placed back into the data if DATAxDMAPRES is set in CRYPTO_SEQCTRL Note that t...

Page 833: ...owing the setup and operation of CBC is explained and illustrated The example can easily be adjusted to perform other cipher block modes EFM32JG1 Reference Manual CRYPTO Crypto Accelerator silabs com Smart Connected Energy friendly Preliminary Rev 0 6 832 ...

Page 834: ...EQ3 RW Sequence Register 3 0x060 CRYPTO_SEQ4 RW Sequence Register 4 0x080 CRYPTO_DATA0 RWH nB a DATA0 Register Access 0x084 CRYPTO_DATA1 RWH nB a DATA1 Register Access 0x088 CRYPTO_DATA2 RWH nB a DATA2 Register Access 0x08C CRYPTO_DATA3 RWH nB a DATA3 Register Access 0x0A0 CRYPTO_DATA0XOR RWH nB a DATA0XOR Register Access 0x0B0 CRYPTO_DATA0BYTE RWH nB a DATA0 Register Byte Access 0x0B4 CRYPTO_DATA...

Page 835: ...148 CRYPTO_DDATA0BYTE32 RWH nB DDATA0 Register Byte 32 access 0x180 CRYPTO_QDATA0 RWH nB a QDATA0 Register Access 0x184 CRYPTO_QDATA1 RWH nB a QDATA1 Register Access 0x1A4 CRYPTO_QDATA1BIG RWH nB a QDATA1 Register Big Endian Access 0x1C0 CRYPTO_QDATA0BYTE RWH nB a QDATA0 Register Byte Access 0x1C4 CRYPTO_QDATA1BYTE RWH nB a QDATA1 Register Byte Access EFM32JG1 Reference Manual CRYPTO Crypto Accele...

Page 836: ... 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0x0 0x0 0x0 0x0 0x0 0 0 0 0 Access RW RW RW RW RW RW RW RW RW RW Name COMBDMA0WEREQ DMA1RSEL DMA1MODE DMA0RSEL DMA0MODE INCWIDTH NOBUSYSTALL SHA KEYBUFDIS AES EFM32JG1 Reference Manual CRYPTO Crypto Accelerator silabs com Smart Connected Energy friendly Preliminary Rev 0 6 835 ...

Page 837: ...re less bytes available than the register size only length 1 bytes necessary zero padding is read Zero padding is au tomatically added when writing 2 FULLBYTE Target register is fully read written during every DMA transaction Byte wise DMA 3 LENLIMITBYTE Length Limited When the current length i e LENGTHA or LENGTHB indicates that there are less bytes available than the register size only length 1 ...

Page 838: ...n 0 INCWIDTH1 Byte 15 in DATA1 is used for the increment function 1 INCWIDTH2 Bytes 14 and 15 in DATA1 are used for the increment function 2 INCWIDTH3 Bytes 13 to 15 in DATA1 are used for the increment function 3 INCWIDTH4 Bytes 12 to 15 in DATA1 are used for the increment function 13 11 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tion...

Page 839: ...0 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 0x0 0 0x0 Access RW RW RW RW Name RESULTWIDTH MULWIDTH MODOP MODULUS EFM32JG1 Reference Manual CRYPTO Crypto Accelerator silabs com Smart Connected Energy friendly Preliminary Rev 0 6 838 ...

Page 840: ...ype Field type used for modular operations Value Mode Description 0 BINARY Modular operations use XOR as required by certain algorithms 1 REGULAR Modular operations use normal modular arithmetic not XOR 3 0 MODULUS 0x0 RW Modular Operation Modulus Modulus used for modular operations Value Mode Description 0 BIN256 Generic modulus p 2 256 1 BIN128 Generic modulus p 2 128 2 ECCBIN233P Modulus for B ...

Page 841: ...3 ECC curve 12 ECCPRIME256N P modulus for P 256 ECC curve 13 ECCPRIME224N P modulus for P 224 ECC curve 14 ECCPRIME192N P modulus for P 192 ECC curve EFM32JG1 Reference Manual CRYPTO Crypto Accelerator silabs com Smart Connected Energy friendly Preliminary Rev 0 6 840 ...

Page 842: ...29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0x00 Access W1 W1 W1 W Name SEQSTEP SEQSTOP SEQSTART INSTR EFM32JG1 Reference Manual CRYPTO Crypto Accelerator silabs com Smart Connected Energy friendly Preliminary Rev 0 6 841 ...

Page 843: ...ow Illegal values are ignored Value Mode Description 0 END End of program 1 EXEC Start executing instructions up to this point which also marks end of program 3 DATA1INC DATA1 inc DATA1 4 DATA1INCCLR DATA1 clearinc DATA1 5 AESENC DATA0 ENC DATA0 KEY BUFFERED KEYBUF KEY 6 AESDEC DATA0 DEC DATA0 7 SHA DDATA0 SHA Q1 8 ADD DDATA0 V0 V1 9 ADDC DDATA0 V0 V1 carry 12 MADD DDATA0 V0 V1 mod P 13 MADD32 DDA...

Page 844: ... DATA0 69 DATA0TODATA2 DATA2 DATA0 70 DATA0TODATA3 DATA3 DATA0 72 DATA1TODATA0 DATA0 DATA1 73 DATA1TODATA0XOR DATA0 DATA0 DATA1 74 DATA1TODATA0XOR LEN DATA0 len 1 0 DATA0 len 1 0 DATA1 len 1 0 77 DATA1TODATA2 DATA2 DATA1 78 DATA1TODATA3 DATA3 DATA1 80 DATA2TODATA0 DATA0 DATA2 81 DATA2TODATA0XOR DATA0 DATA0 DATA2 82 DATA2TODATA0XOR LEN DATA0 len 1 0 DATA0 len 1 0 DATA2 len 1 0 84 DATA2TODATA1 DATA1...

Page 845: ...21 BUFTODATA0XOR DATA0 DATA0 BUFC BUFC buffer defined in READBUFSEL in CRYPTO_CTRL 122 BUFTODATA1 DATA1 BUFC BUFC buffer is defined in READBUFSEL in CRYP TO_CTRL 129 DDATA0TODDATA1 DDATA1 DDATA0 130 DDATA0TODDATA2 DDATA2 DDATA0 131 DDATA0TODDATA3 DDATA3 DDATA0 132 DDATA0TODDATA4 DDATA4 DDATA0 133 DDATA0LTODATA0 DATA0 DDATA0 127 0 134 DDATA0HTODATA1 DATA1 DDATA0 255 128 135 DDATA0LTODATA2 DATA2 DDA...

Page 846: ... DDATA0 as V0 DDATA0 as V1 193 SELDDATA1DDATA0 Use DDATA1 as V0 DDATA0 as V1 194 SELDDATA2DDATA0 Use DDATA2 as V0 DDATA0 as V1 195 SELDDATA3DDATA0 Use DDATA3 as V0 DDATA0 as V1 196 SELDDATA4DDATA0 Use DDATA4 as V0 DDATA0 as V1 197 SELDATA0DDATA0 Use DATA0 as V0 DDATA0 as V1 198 SELDATA1DDATA0 Use DATA1 as V0 DDATA1 as V1 199 SELDATA2DDATA0 Use DATA2 as V0 DDATA2 as V1 200 SELDDATA0DDATA1 Use DDATA...

Page 847: ...26 SELDDATA2DDATA4 Use DDATA2 as V0 DDATA4 as V1 227 SELDDATA3DDATA4 Use DDATA3 as V0 DDATA4 as V1 228 SELDDATA4DDATA4 Use DDATA4 as V0 DDATA4 as V1 229 SELDATA0DDATA4 Use DATA0 as V0 DDATA4 as V1 230 SELDATA1DDATA4 Use DATA1 as V0 DDATA4 as V1 231 SELDATA2DDATA4 Use DATA2 as V0 DDATA4 as V1 232 SELDDATA0DATA0 Use DDATA0 as V0 DATA0 as V1 233 SELDDATA1DATA0 Use DDATA1 as V0 DATA0 as V1 234 SELDDAT...

Page 848: ... 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 Access R R R Name DMAACTIVE INSTRRUNNING SEQRUNNING Bit Name Reset Access Description 31 3 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 2 DMAACTIVE 0 R DMA Action is active This bit indicates that the AES module is waiting for a DMA transfer to complete 1 INSTRRUNNING 0 R Ac...

Page 849: ...RESULTWIDTH in CRYPTO_WAC 19 16 DDATA0MSBS 0xX R MSB in DDATA0 Allows read of 4 MSBs in DDATA0 The bits depend on RESULTWIDTH in CRYPTO_WAC 15 12 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 11 8 DDATA0LSBS 0xX R LSBs in DDATA0 Allows read of 4 LSBs in DDATA0 7 4 Reserved To ensure compatibility with future devices always write bi...

Page 850: ... 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 0 0 0x2 0x1 Access R R R R R Name SEQIP SEQSKIP SEQPART V1 V0 EFM32JG1 Reference Manual CRYPTO Crypto Accelerator silabs com Smart Connected Energy friendly Preliminary Rev 0 6 849 ...

Page 851: ...t A or B of a sequence Value Mode Description 0 SEQA 1 SEQB 15 11 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 10 8 V1 0x2 R Selected ALU Operand 1 Selectable operand for arithmetic operations Value Mode Description 0 DDATA0 1 DDATA1 2 DDATA2 3 DDATA3 4 DDATA4 5 DATA0 6 DATA1 7 DATA2 7 3 Reserved To ensure compatibility with futur...

Page 852: ...te accesses are required to fully read write KEY 25 6 8 CRYPTO_KEYBUF KEY Buffer Register Access No Bit Access Actionable Reads Offset Bit Position 0x024 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0xXXXXXXXX Access RWH Name KEYBUF Bit Name Reset Access Description 31 0 KEYBUF 0xXXXXXXX X RWH Key Buffer Access Access to KEYBUF 4x32bits 8x32bits if AE...

Page 853: ...Skip Set to number of bytes to exclude from data received by next DMA1RD insruction 25 24 DMA0SKIP 0x0 RWH DMA0 Skip Set to number of bytes to exclude from data received by next DMA0RD insruction 23 22 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 21 20 BLOCKSIZE 0x0 RW Size of data blocks Defines the width of blocks processed in e...

Page 854: ...t from CRYPTO again If only the second part of a data set is written enable only this to preserve the data read in during part A 27 14 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 13 0 LENGTHB 0x0000 RWH Buffer length B in bytes Sets the number of bytes to be handled in a second iteration over a programmed sequence 25 6 11 CRYPTO_...

Page 855: ...vices always write bits to 0 More information in 1 2 Conven tions 3 BUFUF 0 W1 Set BUFUF Interrupt Flag Write 1 to set the BUFUF interrupt flag 2 BUFOF 0 W1 Set BUFOF Interrupt Flag Write 1 to set the BUFOF interrupt flag 1 SEQDONE 0 W1 Set SEQDONE Interrupt Flag Write 1 to set the SEQDONE interrupt flag 0 INSTRDONE 0 W1 Set INSTRDONE Interrupt Flag Write 1 to set the INSTRDONE interrupt flag EFM3...

Page 856: ... globally in MSC 2 BUFOF 0 R W1 Clear BUFOF Interrupt Flag Write 1 to clear the BUFOF interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 1 SEQDONE 0 R W1 Clear SEQDONE Interrupt Flag Write 1 to clear the SEQDONE interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags Th...

Page 857: ...le the INSTRDONE interrupt 25 6 15 CRYPTO_SEQ0 Sequence register 0 Offset Bit Position 0x050 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 0x00 0x00 0x00 Access RW RW RW RW Name INSTR3 INSTR2 INSTR1 INSTR0 Bit Name Reset Access Description 31 24 INSTR3 0x00 RW Sequence Instruction 3 Sequence instruction See INSTR the CRYPTO_CMD for a possible valu...

Page 858: ...R the CRYPTO_CMD for a possible values 25 6 17 CRYPTO_SEQ2 Sequence Register 2 Offset Bit Position 0x058 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 0x00 0x00 0x00 Access RW RW RW RW Name INSTR11 INSTR10 INSTR9 INSTR8 Bit Name Reset Access Description 31 24 INSTR11 0x00 RW Sequence Instruction 11 Sequence instruction See INSTR the CRYPTO_CMD for...

Page 859: ...NSTR the CRYPTO_CMD for a possible values 25 6 19 CRYPTO_SEQ4 Sequence Register 4 Offset Bit Position 0x060 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 0x00 0x00 0x00 Access RW RW RW RW Name INSTR19 INSTR18 INSTR17 INSTR16 Bit Name Reset Access Description 31 24 INSTR19 0x00 RW Sequence Instruction 19 Sequence instruction See INSTR the CRYPTO_CM...

Page 860: ...es are required to fully read write DATA0 25 6 21 CRYPTO_DATA1 DATA1 Register Access No Bit Access Actionable Reads Offset Bit Position 0x084 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0xXXXXXXXX Access RWH Name DATA1 Bit Name Reset Access Description 31 0 DATA1 0xXXXXXXX X RWH Data 1 Access Access to DATA1 4x32bits read write accesses are required ...

Page 861: ...es are required to fully read write DATA2 25 6 23 CRYPTO_DATA3 DATA3 Register Access No Bit Access Actionable Reads Offset Bit Position 0x08C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0xXXXXXXXX Access RWH Name DATA3 Bit Name Reset Access Description 31 0 DATA3 0xXXXXXXX X RWH Data 3 Access Access to DATA3 4x32bits read write accesses are required ...

Page 862: ...ite to DATA0 25 6 25 CRYPTO_DATA0BYTE DATA0 Register Byte Access No Bit Access Actionable Reads Offset Bit Position 0x0B0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0xXX Access RWH Name DATA0BYTE Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 7 0...

Page 863: ...r 25 6 27 CRYPTO_DATA0XORBYTE DATA0 Register Byte XOR Access No Bit Access Actionable Reads Offset Bit Position 0x0BC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0xXX Access RWH Name DATA0XORBYTE Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 7 0 ...

Page 864: ... 0 Byte 12 Access Access to DATA0 byte 12 25 6 29 CRYPTO_DATA0BYTE13 DATA0 Register Byte 13 Access No Bit Access Offset Bit Position 0x0C4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0xXX Access RWH Name DATA0BYTE13 Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1...

Page 865: ... 0 Byte 14 Access Access to DATA0 byte 14 25 6 31 CRYPTO_DATA0BYTE15 DATA0 Register Byte 15 Access No Bit Access Offset Bit Position 0x0CC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0xXX Access RWH Name DATA0BYTE15 Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1...

Page 866: ...TA0 25 6 33 CRYPTO_DDATA1 DDATA1 Register Access No Bit Access Actionable Reads Offset Bit Position 0x104 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0xXXXXXXXX Access RWH Name DDATA1 Bit Name Reset Access Description 31 0 DDATA1 0xXXXXXXX X RWH Double Data 0 Access Access to DDATA1 which is equal to the full width of KEY regardless of AES256 in CRYP...

Page 867: ... are required to fully read write DDA TA2 25 6 35 CRYPTO_DDATA3 DDATA3 Register Access No Bit Access Actionable Reads Offset Bit Position 0x10C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0xXXXXXXXX Access RWH Name DDATA3 Bit Name Reset Access Description 31 0 DDATA3 0xXXXXXXX X RWH Double Data 0 Access Access to DDATA3 which consists of DATA3 DATA2 ...

Page 868: ...read write accesses are required to fully read write DDATA4 25 6 37 CRYPTO_DDATA0BIG DDATA0 Register Big Endian Access No Bit Access Actionable Reads Offset Bit Position 0x130 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0xXXXXXXXX Access RWH Name DDATA0BIG Bit Name Reset Access Description 31 0 DDATA0BIG 0xXXXXXXX X RWH Double Data 0 Big Endian Acces...

Page 869: ...tiples of 4 or data incoherency may occur 25 6 39 CRYPTO_DDATA1BYTE DDATA1 Register Byte Access No Bit Access Actionable Reads Offset Bit Position 0x144 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0xXX Access RWH Name DDATA1BYTE Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More inf...

Page 870: ...ess to DDATA0 byte 32 This is used when RESULTWIDTH in CRYPTO_WAC is set to 260BIT 25 6 41 CRYPTO_QDATA0 QDATA0 Register Access No Bit Access Actionable Reads Offset Bit Position 0x180 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0xXXXXXXXX Access RWH Name QDATA0 Bit Name Reset Access Description 31 0 QDATA0 0xXXXXXXX X RWH Quad Data 0 Access Access t...

Page 871: ...ly read write QDATA1 25 6 43 CRYPTO_QDATA1BIG QDATA1 Register Big Endian Access No Bit Access Actionable Reads Offset Bit Position 0x1A4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0xXXXXXXXX Access RWH Name QDATA1BIG Bit Name Reset Access Description 31 0 QDATA1BIG 0xXXXXXXX X RWH Quad Data 1 Big Endian Access Big endian access to QDATA1 which is eq...

Page 872: ...tiples of 4 or data incoherency may occur 25 6 45 CRYPTO_QDATA1BYTE QDATA1 Register Byte Access No Bit Access Actionable Reads Offset Bit Position 0x1C4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0xXX Access RWH Name QDATA1BYTE Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More inf...

Page 873: ...asynchronous interrupts can also be generated from any pin 26 1 Introduction In the EFM32 Jade Gecko devices the General Purpose Input Output GPIO pins are organized into ports with up to 16 pins each These GPIO pins can individually be configured as either an output or input More advanced configurations like open drain open source and glitch filtering can be configured for each individual GPIO pi...

Page 874: ... overridden by peripheral Output enable can be overridden by peripheral Toggle register for output data Dedicated data input register read only Interrupts 2 Interrupt lines using either levels or edges EM4 wake up pins are selectable for level interrupts All GPIO pins are selectable for edge interrups Separate enable status set and clear registers Asynchronous sensing Rising falling or both edges ...

Page 875: ...gister is connected to pin n on the port When configured as an output the value of the Data Out Register GPIO_Px_DOUT will be driven to the pin The DOUT value can be changed in 4 different ways Writing to the GPIO_Px_DOUT register Writing the BITSET address of the GPIO_Px_DOUT register sets the DOUT bits Writing the BITCLEAR address of the GPIO_Px_DOUT register clears the DOUT bits Writing the GPI...

Page 876: ...pen source WIREDORPULLDOWN x On Open source with pull down WIREDAND Open Drain Wired AND x Open drain WIREDANDFILTER x On Open drain with filter WIREDANDPULLUP x On Open drain with pull up WIREDANDPULLUPFILTER x On On Open drain with pull up and filter WIREDANDALT x On Open drain with alternate port control values WIREDANDALTFILTER x On On Open drain with alternate port control values and fil ter ...

Page 877: ...ODEn is WIREDOR or WIREDORPULLDOWN the pin operates in open source mode with a pull down resistor for WIRE DORPULLDOWN When driving a high value in open source mode the pull down is disconnected to save power When the mode is prefixed with WIREDAND the pin operates in open drain mode as shown in Figure 26 4 Open drain on page 876 In open drain mode the pin can have an input filter a pull up altern...

Page 878: ... can be applied to pins on a port by port basis The drive strength applied to pins configured using normal MODEn settings can be controlled using the DRIVESTRENGTH field in GPIO_Px_CTRL The drive strength applied to pins configured using alternate MODEn settings can be controled using the DRIVESTRENGTHALT field 26 3 1 4 Slewrate The slewrate can be applied to pins on a port by port basis The slewr...

Page 879: ...F register The mapping between EM4WU pins and the bit indexes in the GPIO_EM4WUEN GPIO_EXTILEVEL GPIO_IFC GPIO_IFS GPIO_IEN and GPIO_IF registers is as follows Table 26 2 EM4WU Register Bit Index to EM4WU pin Mapping EM4WU Register Bit Indexes EM4WU Pin 16 GPIO_EM4WU0 17 GPIO_EM4WU1 18 GPIO_EM4WU2 19 GPIO_EM4WU3 31 GPIO_EM4WU15 Note Please see the device datasheet for actual pin location 26 3 3 EM...

Page 880: ...pull up and pull down resistors respectivlely It is possible to disable these pin connections and disable the pull resistors by setting the SWDIOTMSPEN and SWCLKTCKPEN bits in GPIO_ROUTEPEN to 0 The Serial Wire Viewer pin SWV can be enabled by setting the SWVPEN bit in GPIO_ROUTEPEN This bit can also be routed to alternate locations by configuring the SWVLOC bitfield in GPIO_ROUTELOC0 26 3 4 2 2 J...

Page 881: ...s in GPIO_EXTIPSELL or GPIO_EXTIPSELH select which PORT in the group will trigger the interupt The EXTI PINSELn bits in GPIO_EXTIPINSELL or GPIO_EXTIPINSELH will determine which pin inside the selected group will trigger the inter rupt For example if EXTIPSEL11 PORTB and EXTPINSEL11 0 then PB8 will be used for EXTI11 EXTI11 uses the third group 11 4 2 so the list of possible pins is Px 11 8 The se...

Page 882: ... be triggered by a high level on pin EM4WU8 and a interrupt request will be sent on IRQ_GPIO_EVEN Figure 26 7 Level Interrupt Example 26 3 6 Output to PRS All pins within a group of four 0 3 4 7 8 11 12 15 from all ports are grouped together to form one PRS producer which outputs to the PRS The pin from which the output should be taken is selected in the same fashion as the edge interrupts PRS out...

Page 883: ...F_MODEL RW Port Pin Mode Low Register 0x0F8 GPIO_PF_MODEH RW Port Pin Mode High Register 0x0FC GPIO_PF_DOUT RW Port Data Out Register 0x108 GPIO_PF_DOUTTGL W1 Port Data Out Toggle Register 0x10C GPIO_PF_DIN R Port Data In Register 0x110 GPIO_PF_PINLOCKN RW Port Unlocked Pins Register 0x118 GPIO_PF_OVTDIS RW Over Voltage Disable for all modes 0x400 GPIO_EXTIPSELL RW External Interrupt Port Select L...

Page 884: ...I O Routing Pin Enable Register 0x444 GPIO_ROUTELOC0 RW I O Routing Location Register 0x450 GPIO_INSENSE RW Input Sense Register 0x454 GPIO_LOCK RWH Configuration Lock Register EFM32JG1 Reference Manual GPIO General Purpose Input Output silabs com Smart Connected Energy friendly Preliminary Rev 0 6 883 ...

Page 885: ...5 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0x5 0 0 0x5 0 Access RW RW RW RW RW RW Name DINDISALT SLEWRATEALT DRIVESTRENGTHALT DINDIS SLEWRATE DRIVESTRENGTH EFM32JG1 Reference Manual GPIO General Purpose Input Output silabs com Smart Connected Energy friendly Preliminary Rev 0 6 884 ...

Page 886: ...lue Mode Description 0 STRONG 10 mA drive current 1 WEAK 1 mA drive current 15 13 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 12 DINDIS 0 RW Data In Disable Data input disable for port pins not using alternate modes 11 7 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tio...

Page 887: ... 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access RW RW RW RW RW RW RW RW Name MODE7 MODE6 MODE5 MODE4 MODE3 MODE2 MODE1 MODE0 EFM32JG1 Reference Manual GPIO General Purpose Input Output silabs com Smart Connected Energy friendly Preliminary Rev 0 6 886 ...

Page 888: ...using alternate control with filter 14 WIREDANDALTPULL UP Open drain output using alternate control with pullup 15 WIREDANDALTPUL LUPFILTER Open drain output uisng alternate control with filter and pullup 27 24 MODE6 0x0 RW Pin 6 Mode Configure mode for pin 6 Value Mode Description 0 DISABLED Input disabled Pullup if DOUT is set 1 INPUT Input enabled Filter if DOUT is set 2 INPUTPULL Input enabled...

Page 889: ...drain output 9 WIREDANDFILTER Open drain output with filter 10 WIREDANDPULLUP Open drain output with pullup 11 WIREDANDPULLUP FILTER Open drain output with filter and pullup 12 WIREDANDALT Open drain output using alternate control 13 WIREDANDALTFILTER Open drain output using alternate control with filter 14 WIREDANDALTPULL UP Open drain output using alternate control with pullup 15 WIREDANDALTPUL ...

Page 890: ...UTPULLFILTER Input enabled with filter DOUT determines pull direction 4 PUSHPULL Push pull output 5 PUSHPULLALT Push pull using alternate control 6 WIREDOR Wired or output 7 WIREDORPULLDOWN Wired or output with pull down 8 WIREDAND Open drain output 9 WIREDANDFILTER Open drain output with filter 10 WIREDANDPULLUP Open drain output with pullup 11 WIREDANDPULLUP FILTER Open drain output with filter ...

Page 891: ...onfigure mode for pin 1 Value Mode Description 0 DISABLED Input disabled Pullup if DOUT is set 1 INPUT Input enabled Filter if DOUT is set 2 INPUTPULL Input enabled DOUT determines pull direction 3 INPUTPULLFILTER Input enabled with filter DOUT determines pull direction 4 PUSHPULL Push pull output 5 PUSHPULLALT Push pull using alternate control 6 WIREDOR Wired or output 7 WIREDORPULLDOWN Wired or ...

Page 892: ...OWN Wired or output with pull down 8 WIREDAND Open drain output 9 WIREDANDFILTER Open drain output with filter 10 WIREDANDPULLUP Open drain output with pullup 11 WIREDANDPULLUP FILTER Open drain output with filter and pullup 12 WIREDANDALT Open drain output using alternate control 13 WIREDANDALTFILTER Open drain output using alternate control with filter 14 WIREDANDALTPULL UP Open drain output usi...

Page 893: ... 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access RW RW RW RW RW RW RW RW Name MODE15 MODE14 MODE13 MODE12 MODE11 MODE10 MODE9 MODE8 EFM32JG1 Reference Manual GPIO General Purpose Input Output silabs com Smart Connected Energy friendly Preliminary Rev 0 6 892 ...

Page 894: ...using alternate control with filter 14 WIREDANDALTPULL UP Open drain output using alternate control with pullup 15 WIREDANDALTPUL LUPFILTER Open drain output uisng alternate control with filter and pullup 27 24 MODE14 0x0 RW Pin 14 Mode Configure mode for pin 14 Value Mode Description 0 DISABLED Input disabled Pullup if DOUT is set 1 INPUT Input enabled Filter if DOUT is set 2 INPUTPULL Input enab...

Page 895: ...drain output 9 WIREDANDFILTER Open drain output with filter 10 WIREDANDPULLUP Open drain output with pullup 11 WIREDANDPULLUP FILTER Open drain output with filter and pullup 12 WIREDANDALT Open drain output using alternate control 13 WIREDANDALTFILTER Open drain output using alternate control with filter 14 WIREDANDALTPULL UP Open drain output using alternate control with pullup 15 WIREDANDALTPUL ...

Page 896: ...UTPULLFILTER Input enabled with filter DOUT determines pull direction 4 PUSHPULL Push pull output 5 PUSHPULLALT Push pull using alternate control 6 WIREDOR Wired or output 7 WIREDORPULLDOWN Wired or output with pull down 8 WIREDAND Open drain output 9 WIREDANDFILTER Open drain output with filter 10 WIREDANDPULLUP Open drain output with pullup 11 WIREDANDPULLUP FILTER Open drain output with filter ...

Page 897: ...onfigure mode for pin 9 Value Mode Description 0 DISABLED Input disabled Pullup if DOUT is set 1 INPUT Input enabled Filter if DOUT is set 2 INPUTPULL Input enabled DOUT determines pull direction 3 INPUTPULLFILTER Input enabled with filter DOUT determines pull direction 4 PUSHPULL Push pull output 5 PUSHPULLALT Push pull using alternate control 6 WIREDOR Wired or output 7 WIREDORPULLDOWN Wired or ...

Page 898: ...output with filter and pullup 12 WIREDANDALT Open drain output using alternate control 13 WIREDANDALTFILTER Open drain output using alternate control with filter 14 WIREDANDALTPULL UP Open drain output using alternate control with pullup 15 WIREDANDALTPUL LUPFILTER Open drain output uisng alternate control with filter and pullup 26 5 4 GPIO_Px_DOUT Port Data Out Register Offset Bit Position 0x00C ...

Page 899: ... bits to 1 to toggle corresponding bits in GPIO_Px_DOUT Bits written to 0 will have no effect 26 5 6 GPIO_Px_DIN Port Data In Register Offset Bit Position 0x01C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 Access R Name DIN Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More i...

Page 900: ...e pin is then locked until reset 26 5 8 GPIO_Px_OVTDIS Over Voltage Disable for all modes Offset Bit Position 0x028 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 Access RW Name OVTDIS Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 15 0 OVTDI...

Page 901: ...19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access RW RW RW RW RW RW RW RW Name EXTIPSEL7 EXTIPSEL6 EXTIPSEL5 EXTIPSEL4 EXTIPSEL3 EXTIPSEL2 EXTIPSEL1 EXTIPSEL0 EFM32JG1 Reference Manual GPIO General Purpose Input Output silabs com Smart Connected Energy friendly Preliminary Rev 0 6 900 ...

Page 902: ...EXTIPSEL5 0x0 RW External Interrupt 5 Port Select Select input port for external interrupt 5 Value Mode Description 0 PORTA Port A group selected for external interrupt 5 1 PORTB Port B group selected for external interrupt 5 2 PORTC Port C group selected for external interrupt 5 3 PORTD Port D group selected for external interrupt 5 5 PORTF Port F group selected for external interrupt 5 19 16 EXT...

Page 903: ...XTIPSEL1 0x0 RW External Interrupt 1 Port Select Select input port for external interrupt 1 Value Mode Description 0 PORTA Port A group selected for external interrupt 1 1 PORTB Port B group selected for external interrupt 1 2 PORTC Port C group selected for external interrupt 1 3 PORTD Port D group selected for external interrupt 1 5 PORTF Port F group selected for external interrupt 1 3 0 EXTIPS...

Page 904: ... 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access RW RW RW RW RW RW RW RW Name EXTIPSEL15 EXTIPSEL14 EXTIPSEL13 EXTIPSEL12 EXTIPSEL11 EXTIPSEL10 EXTIPSEL9 EXTIPSEL8 EFM32JG1 Reference Manual GPIO General Purpose Input Output silabs com Smart Connected Energy friendly Preliminary Rev 0 6 903 ...

Page 905: ...TIPSEL13 0x0 RW External Interrupt 13 Port Select Select input port for external interrupt 13 Value Mode Description 0 PORTA Port A group selected for external interrupt 13 1 PORTB Port B group selected for external interrupt 13 2 PORTC Port C group selected for external interrupt 13 3 PORTD Port D group selected for external interrupt 13 5 PORTF Port F group selected for external interrupt 13 19 ...

Page 906: ...0 7 4 EXTIPSEL9 0x0 RW External Interrupt 9 Port Select Select input port for external interrupt 9 Value Mode Description 0 PORTA Port A group selected for external interrupt 9 1 PORTB Port B group selected for external interrupt 9 2 PORTC Port C group selected for external interrupt 9 3 PORTD Port D group selected for external interrupt 9 5 PORTF Port F group selected for external interrupt 9 3 0...

Page 907: ...7 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x3 0x2 0x1 0x0 0x3 0x2 0x1 0x0 Access RW RW RW RW RW RW RW RW Name EXTIPINSEL7 EXTIPINSEL6 EXTIPINSEL5 EXTIPINSEL4 EXTIPINSEL3 EXTIPINSEL2 EXTIPINSEL1 EXTIPINSEL0 EFM32JG1 Reference Manual GPIO General Purpose Input Output silabs com Smart Connected Energy friendly Preliminary Rev 0 6 906 ...

Page 908: ...on 0 PIN4 Pin 4 1 PIN5 Pin 5 2 PIN6 Pin 6 3 PIN7 Pin 7 23 22 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 21 20 EXTIPINSEL5 0x1 RW External Interrupt 5 Pin Select Select the pin for external interrupt 5 Value Mode Description 0 PIN4 Pin 4 1 PIN5 Pin 5 2 PIN6 Pin 6 3 PIN7 Pin 7 19 18 Reserved To ensure compatibility with future dev...

Page 909: ...ption 0 PIN0 Pin 0 1 PIN1 Pin 1 2 PIN2 Pin 2 3 PIN3 Pin 3 7 6 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 5 4 EXTIPINSEL1 0x1 RW External Interrupt 1 Pin Select Select the pin for external interrupt 1 Value Mode Description 0 PIN0 Pin 0 1 PIN1 Pin 1 2 PIN2 Pin 2 3 PIN3 Pin 3 3 2 Reserved To ensure compatibility with future device...

Page 910: ...6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x3 0x2 0x1 0x0 0x3 0x2 0x1 0x0 Access RW RW RW RW RW RW RW RW Name EXTIPINSEL15 EXTIPINSEL14 EXTIPINSEL13 EXTIPINSEL12 EXTIPINSEL11 EXTIPINSEL10 EXTIPINSEL9 EXTIPINSEL8 EFM32JG1 Reference Manual GPIO General Purpose Input Output silabs com Smart Connected Energy friendly Preliminary Rev 0 6 909 ...

Page 911: ...12 Pin 12 1 PIN13 Pin 13 2 PIN14 Pin 14 3 PIN15 Pin 15 23 22 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 21 20 EXTIPINSEL13 0x1 RW External Interrupt 13 Pin Select Select the pin for external interrupt 13 Value Mode Description 0 PIN12 Pin 12 1 PIN13 Pin 13 2 PIN14 Pin 14 3 PIN15 Pin 15 19 18 Reserved To ensure compatibility with...

Page 912: ...tion 0 PIN8 Pin 8 1 PIN9 Pin 9 2 PIN10 Pin 10 3 PIN11 Pin 11 7 6 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 5 4 EXTIPINSEL9 0x1 RW External Interrupt 9 Pin Select Select the pin for external interrupt 9 Value Mode Description 0 PIN8 Pin 8 1 PIN9 Pin 9 2 PIN10 Pin 10 3 PIN11 Pin 11 3 2 Reserved To ensure compatibility with future...

Page 913: ...E n 1 Rising edge trigger ena bled 26 5 14 GPIO_EXTIFALL External Interrupt Falling Edge Trigger Register Offset Bit Position 0x414 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 Access RW Name EXTIFALL Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conve...

Page 914: ...nformation in 1 2 Conven tions 25 EM4WU9 0 RW EM4 Wake Up Level for EM4WU9 Pin 24 EM4WU8 0 RW EM4 Wake Up Level for EM4WU8 Pin 23 21 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 20 EM4WU4 0 RW EM4 Wake Up Level for EM4WU4 Pin 19 18 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 ...

Page 915: ...ernal interrupt flag Value Description 0 External interrupt flag cleared 1 External interrupt flag set 26 5 17 GPIO_IFS Interrupt Flag Set Register Offset Bit Position 0x420 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 0x0000 Access W1 W1 Name EM4WU EXT Bit Name Reset Access Description 31 16 EM4WU 0x0000 W1 Set EM4WU Interrupt Flag Write 1 to ...

Page 916: ...Interrupt Flag Write 1 to clear the EXT interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 26 5 19 GPIO_IEN Interrupt Enable Register Offset Bit Position 0x428 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 0x0000 Access RW RW Name EM4WU EXT Bit Name Reset A...

Page 917: ...16 EM4WUEN 0x0000 RW EM4 wake up enable Write 1 to enable EM4 wake up request write 0 to disable EM4 wake up request Value Description 0 Disable EM4 wake up on pin 1 Enable EM4 wake up on pin 15 0 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions EFM32JG1 Reference Manual GPIO General Purpose Input Output silabs com Smart Connected Ene...

Page 918: ...to pin WARNING When this pin is disabled the device can no longer be accessed by a debugger A reset will set the pin back to a default state as enabled If you disable this pin make sure you have at least a 3 second timeout at the start of you program code before you disable the pin This way the debugger will have time to halt the device after a reset before the pin is disabled 0 SWCLKTCKPEN 1 RW S...

Page 919: ... Location 2 3 LOC3 Location 3 26 5 23 GPIO_INSENSE Input Sense Register Offset Bit Position 0x450 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 1 1 Access RW RW Name EM4WU INT Bit Name Reset Access Description 31 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 1 EM4WU 1 RW EM4WU Interru...

Page 920: ...ck Key Write any other value than the unlock code to lock MODEL MODEH CTRL PINLOCKN OVTDIS EXTIPSELL EXTIP SELH EXTIGSELL EXTIGSELH INSENSE ROUTEPEN and ROUTELOC0 from editing Write the unlock code to unlock When reading the register bit 0 is set when the lock is enabled Mode Value Description Read Operation UNLOCKED 0 GPIO registers are unlocked LOCKED 1 GPIO registers are locked Write Operation ...

Page 921: ... switches the pad and the analog signal onto a common bus 27 1 Introduction APORT consists of wires switches and control logic needed to route signals between analog peripherals and I O pins On chip clients can be either producers or consumers Analog producers are active devices that drive current voltage into an APORT such as current or voltage DACs Consumers are passive devices that monitor or r...

Page 922: ...Since many clients can operate differentially buses are grouped by pairs as X and Y If a given client uses a single ABUS e g single ended ADC X and Y are just labels to differentiate the two buses When operating differentially most APORT clients require that one input be chosen from an X bus and the other from a Y bus For example the ACMP block will not allow both positive and negative inputs to b...

Page 923: ...e pair For example APDX decodes as AP APORT D pair X bus Figure 27 2 APORT Structure on page 922 illustrates this organization APORT clients are generally described in this reference manual For example the ACMP client is described once but the device could contain multiple instances of the ACMP Because of this for APORT client descriptions in this reference manual the ABUS connections are generali...

Page 924: ...has multiple switches which need to be identified The switches on a bus are specified with the bus name ID followed by a channel ID For example channel switch 7 on a given APORT client might be given as BUS1XCH7 Channels are not always map to an I O for a particular device Refer to the APORT Client Map in the device datasheet for which channels are mapped and if mapped to which I O EFM32JG1 Refere...

Page 925: ...le if an IDAC ADC and ACMP all want to use the same pin on a particular ABUS the user might set the bus master disable bit to 1 for the IDAC and ACMP The ADC is the sole master of the switch configuration on that ABUS so switches are configured using the configuration set in the ADC ACMP0 ABUS 0 ABUS 2 ABUS 4 ABUS 6 ABUS 1 ABUS 3 ABUS 5 ABUS 7 ACMP1 ADC0 APORT_CONTROL ABUS_REQ 0000_1111 ABUS_REQ 0...

Page 926: ...ient ABUS 0 The user must resolve the conflict before ABUS 0 is useable ACMP0 ABUS 0 ABUS 2 ABUS 4 ABUS 6 ABUS 1 ABUS 3 ABUS 5 ABUS 7 ACMP1 ADC0 APORT_CONTROL ABUS_REQ 0000_1111 ABUS_REQ 0011_0000 ABUS_REQ 0000_0000 Figure 27 5 APORT Example 3 Sharing an ABUS Figure 27 5 APORT Example 3 Sharing an ABUS on page 925 illustrates ABUS sharing Both ACMPs are configured identically ex cept ACMP0 has its...

Page 927: ...Code AES mode of operation CC Compare Capture CFB Cipher Feedback AES mode of operation CLK Clock CMD Command CMU Clock Management Unit CM3 ARM Cortex M3 CM4 ARM Cortex M4 CRC Cyclic Redundancy Check CTR Counter mode AES mode of operation CTRL Control DBG Debug DC Direct Current ECB Electronic Code Book AES mode of operation EFM32 Energy Frendly Microcontroller EM Energy Mode EMU Energy Management...

Page 928: ... of operation PD Power Down PRS Peripheral Reflex System PWM Pulse Width Modulation RAM Random Access Memory RMU Reset Management Unit RTC Real Time Counter RX Receive SPI Serial Peripheral Interface SW Software TX Transmit XTAL Crystal EFM32JG1 Reference Manual Abbreviations silabs com Smart Connected Energy friendly Preliminary Rev 0 6 927 ...

Page 929: ...aneous Interrupts 12 3 3 1 2 IFC Read clear Operation 12 3 3 2 Interrupt Request Lines IRQ 13 4 Memory and Bus System 14 4 1 Introduction 14 4 2 Functional Description 15 4 2 1 Bit banding 17 4 2 2 Peripheral Bit Set and Clear 18 4 2 3 Peripherals 19 4 2 4 Bus Matrix 19 4 2 4 1 Arbitration 20 4 2 4 2 Access Performance 20 4 2 4 3 Bus Faults 21 4 3 Access to Low Energy Peripherals Asynchronous Regi...

Page 930: ...HFRCOCAL12 HFRCO Calibration Register 38 MHz 42 4 7 24 AUXHFRCOCAL0 AUXHFRCO Calibration Register 4 MHz 43 4 7 25 AUXHFRCOCAL3 AUXHFRCO Calibration Register 7 MHz 44 4 7 26 AUXHFRCOCAL6 AUXHFRCO Calibration Register 13 MHz 45 4 7 27 AUXHFRCOCAL7 AUXHFRCO Calibration Register 16 MHz 46 4 7 28 AUXHFRCOCAL8 AUXHFRCO Calibration Register 19 MHz 47 4 7 29 AUXHFRCOCAL10 AUXHFRCO Calibration Register 26 ...

Page 931: ... 8 AAP_CRCRESULT CRC Result Register 68 5 5 9 AAP_IDR AAP Identification Register 68 6 MSC Memory System Controller 69 6 1 Introduction 69 6 2 Features 70 6 3 Functional Description 71 6 3 1 User Data UD Page Description 71 6 3 2 Lock Bits LB Page Description 72 6 3 3 Device Information DI Page 72 6 3 4 Bootloader 72 6 3 5 Device Revision 73 6 3 6 Post reset Behavior 73 6 3 7 Flash Startup 73 6 3 ...

Page 932: ... 1 1 Features 95 7 2 Block Diagram 96 7 3 Functional Description 97 7 3 1 Channel Descriptor 97 7 3 1 1 DMA Transfer Size 97 7 3 1 2 Source Destination Increments 97 7 3 1 3 Block Size 97 7 3 1 4 Transfer Count 98 7 3 1 5 Descriptor List 98 7 3 1 6 Addresses 98 7 3 1 7 Addressing Modes 98 7 3 1 8 Byte Swap 99 7 3 1 9 DMA Size and Source Destination Increment Programming 100 7 3 2 Channel Configura...

Page 933: ...k Load Register 127 7 6 12 LDMA_REQCLEAR DMA Channel Request Clear Register 127 7 6 13 LDMA_IF Interrupt Flag Register 128 7 6 14 LDMA_IFS Interrupt Flag Set Register 128 7 6 15 LDMA_IFC Interrupt Flag Clear Register 129 7 6 16 LDMA_IEN Interrupt Enable register 129 7 6 17 LDMA_CHx_REQSEL Channel Peripheral Request Select Register 130 7 6 18 LDMA_CHx_CFG Channel Configuration Register 133 7 6 19 L...

Page 934: ... into EM4 Hibernate 161 9 3 3 Exiting a Low Energy Mode 162 9 3 4 Power Configurations 163 9 3 4 1 Power Configuration 0 STARTUP 164 9 3 4 2 Power Configuration 1 No DC DC 165 9 3 4 3 Power Configuration 2 DC DC 166 9 3 5 DC to DC Interface 166 9 3 5 1 Bypass Mode 167 9 3 5 2 Low Power LP Mode 167 9 3 5 3 Low Noise LN Mode 167 9 3 5 4 Analog Peripheral Power Selection 168 9 3 5 5 IOVDD Connection ...

Page 935: ...EMU_DCDCLPCTRL DCDC Low Power Control Register 199 9 5 24 EMU_DCDCLNFREQCTRL DCDC Low Noise Controller Frequency Control 200 9 5 25 EMU_DCDCSYNC DCDC Read Status Register 200 9 5 26 EMU_VMONAVDDCTRL VMON AVDD Channel Control 201 9 5 27 EMU_VMONALTAVDDCTRL Alternate VMON AVDD Channel Control 202 9 5 28 EMU_VMONDVDDCTRL VMON DVDD Channel Control 203 9 5 29 EMU_VMONIO0CTRL VMON IOVDD0 Channel Control...

Page 936: ... Command Register 254 10 5 14 CMU_CMD Command Register 255 10 5 15 CMU_DBGCLKSEL Debug Trace Clock Select 256 10 5 16 CMU_HFCLKSEL High Frequency Clock Select Command Register 256 10 5 17 CMU_LFACLKSEL Low Frequency A Clock Select Register 257 10 5 18 CMU_LFBCLKSEL Low Frequency B Clock Select Register 257 10 5 19 CMU_LFECLKSEL Low Frequency E Clock Select Register 258 10 5 20 CMU_STATUS Status Re...

Page 937: ...nels 295 11 3 3 Interrupts and PRS Output 297 11 3 3 1 Main Counter Tick PRS Output 298 11 3 4 Energy Mode Availability 298 11 3 5 Register Lock 298 11 3 6 Oscillator Failure Detection 298 11 3 7 Retention Registers 298 11 3 8 Frame Controller Interface 298 11 3 9 Debug Session 298 11 4 Register Map 299 11 5 Register Description 300 11 5 1 RTCC_CTRL Control Register Async Reg 300 11 5 2 RTCC_PRECN...

Page 938: ... 324 12 5 2 WDOG_CMD Command Register Async Reg 328 12 5 3 WDOG_SYNCBUSY Synchronization Busy Register 328 12 5 4 WDOGn_PCHx_PRSCTRL PRS Control Register Async Reg 329 12 5 5 WDOG_IF Watchdog Interrupt Flags 330 12 5 6 WDOG_IFS Interrupt Flag Set Register 331 12 5 7 WDOG_IFC Interrupt Flag Clear Register 332 12 5 8 WDOG_IEN Interrupt Enable Register 333 13 PRS Peripheral Reflex System 334 13 1 Int...

Page 939: ...7 Input Filter 372 14 3 8 Edge Polarity 373 14 3 9 PRS and PCNTn_S0IN PCNTn_S1IN Inputs 373 14 3 10 Interrupts 373 14 3 10 1 Underflow and Overflow Interrupts 373 14 3 10 2 Direction Change Interrupt 374 14 3 11 Cascading Pulse Counters 375 14 4 Register Map 376 14 5 Register Description 377 14 5 1 PCNTn_CTRL Control Register Async Reg 377 14 5 2 PCNTn_CMD Command Register Async Reg 381 14 5 3 PCN...

Page 940: ...7 3 Automatic ACK Interaction 407 15 3 7 4 Reset State 407 15 3 7 5 Master Transmitter 408 15 3 7 6 Master Receiver 410 15 3 8 Bus States 412 15 3 9 Slave Operation 412 15 3 9 1 Slave State Machine 413 15 3 9 2 Address Recognition 413 15 3 9 3 Slave Transmitter 414 15 3 9 4 Slave Receiver 416 15 3 10 Transfer Automation 416 15 3 10 1 DMA 417 15 3 10 2 Automatic ACK 417 15 3 10 3 Automatic STOP 417...

Page 941: ...chronous Asynchronous Receiver Transmitter 447 16 1 Introduction 447 16 2 Features 448 16 3 Functional Description 449 16 3 1 Modes of Operation 450 16 3 2 Asynchronous Operation 450 16 3 2 1 Frame Format 451 16 3 2 2 Parity bit Calculation and Handling 452 16 3 2 3 Clock Generation 453 16 3 2 4 Auto Baud Detection 454 16 3 2 5 Data Transmission 454 16 3 2 6 Transmit Buffer Operation 455 16 3 2 7 ...

Page 942: ... Trigger Control register 491 16 5 4 USARTn_CMD Command Register 494 16 5 5 USARTn_STATUS USART Status Register 495 16 5 6 USARTn_CLKDIV Clock Control Register 497 16 5 7 USARTn_RXDATAX RX Buffer Data Extended Register Actionable Reads 498 16 5 8 USARTn_RXDATA RX Buffer Data Register Actionable Reads 498 16 5 9 USARTn_RXDOUBLEX RX Buffer Double Data Extended Register Actionable Reads 499 16 5 10 U...

Page 943: ... 4 2 Frame Transmission Control 546 17 3 5 Data Reception 547 17 3 5 1 Receive Buffer Operation 547 17 3 5 2 Blocking Incoming Data 548 17 3 5 3 Data Sampling 548 17 3 5 4 Parity Error 548 17 3 5 5 Framing Error and Break Detection 549 17 3 5 6 Programmable Start Frame 549 17 3 5 7 Programmable Signal Frame 549 17 3 5 8 Multi Processor Mode 550 17 3 6 Loopback 550 17 3 7 Half Duplex Communication ...

Page 944: ... Introduction 578 18 2 Features 579 18 3 Functional Description 580 18 3 1 Counter Modes 580 18 3 1 1 Events 581 18 3 1 2 Operation 581 18 3 1 3 Clock Source 582 18 3 1 4 Peripheral Clock HFPERCLK 582 18 3 1 5 Compare Capture Channel 1 Input 582 18 3 1 6 Underflow Overflow from Neighboring Timer 582 18 3 1 7 One Shot Mode 582 18 3 1 8 Top Value Buffer 583 18 3 1 9 Quadrature Decoder 584 18 3 1 10 ...

Page 945: ...5 14 TIMERn_ROUTELOC2 I O Routing Location Register 624 18 5 15 TIMERn_CCx_CTRL CC Channel Control Register 628 18 5 16 TIMERn_CCx_CCV CC Channel Value Register Actionable Reads 631 18 5 17 TIMERn_CCx_CCVP CC Channel Value Peek Register 632 18 5 18 TIMERn_CCx_CCVB CC Channel Buffer Register 632 18 5 19 TIMERn_DTCTRL DTI Control Register 633 18 5 20 TIMERn_DTTIME DTI Time Control Register 636 18 5 ...

Page 946: ...ETIMERn_IFC Interrupt Flag Clear Register 667 19 5 12 LETIMERn_IEN Interrupt Enable Register 668 19 5 13 LETIMERn_SYNCBUSY Synchronization Busy Register 668 19 5 14 LETIMERn_ROUTEPEN I O Routing Pin Enable Register 669 19 5 15 LETIMERn_ROUTELOC0 I O Routing Location Register 670 19 5 16 LETIMERn_PRSSEL PRS Input Select Register 673 20 CRYOTIMER Ultra Low Energy Timer Counter 677 20 1 Introduction ...

Page 947: ...RTCONFLICT APORT Conflict Status Register 710 21 5 10 ACMPn_HYSTERESIS0 Hysteresis 0 Register 712 21 5 11 ACMPn_HYSTERESIS1 Hysteresis 1 Register 713 21 5 12 ACMPn_ROUTEPEN I O Routing Pine Enable Register 714 21 5 13 ACMPn_ROUTELOC0 I O Routing Location Register 715 22 ADC Analog to Digital Converter 717 22 1 Introduction 717 22 2 Features 718 22 3 Functional Description 719 22 3 1 Clock Selectio...

Page 948: ...r 761 22 5 9 ADCn_SCANINPUTSEL Input Selection register for Scan mode 764 22 5 10 ADCn_SCANNEGSEL Negative Input select register for Scan 767 22 5 11 ADCn_CMPTHR Compare Threshold Register 770 22 5 12 ADCn_BIASPROG Bias Programming Register for various analog blocks used in ADC opera tion 771 22 5 13 ADCn_CAL Calibration Register 772 22 5 14 ADCn_IF Interrupt Flag Register 774 22 5 15 ADCn_IFS Int...

Page 949: ...g Register 799 23 5 3 IDAC_DUTYCONFIG Duty Cycle Configauration Register 800 23 5 4 IDAC_STATUS Status Register 800 23 5 5 IDAC_IF Interrupt Flag Register 801 23 5 6 IDAC_IFS Interrupt Flag Set Register 801 23 5 7 IDAC_IFC Interrupt Flag Clear Register 802 23 5 8 IDAC_IEN Interrupt Enable Register 802 23 5 9 IDAC_APORTREQ APORT Request Status Register 803 23 5 10 IDAC_APORTCONFLICT APORT Request S...

Page 950: ... 3 Repeated Sequence 826 25 4 4 AES 827 25 4 5 SHA 829 25 4 6 ECC 829 25 4 7 GCM and GMAC 830 25 4 8 DMA 830 25 4 8 1 DMA Initial Bytes Skip 831 25 4 8 2 DMA Unaligned Read Write 831 25 4 10 Debugging 831 25 4 11 Example Cipher Block Chaining CBC 832 25 5 Register Map 833 25 6 Register Description 835 25 6 1 CRYPTO_CTRL Control Register 835 25 6 2 CRYPTO_WAC Wide Arithmetic Configuration 838 25 6 ...

Page 951: ...Reads 865 25 6 33 CRYPTO_DDATA1 DDATA1 Register Access No Bit Access Actionable Reads 865 25 6 34 CRYPTO_DDATA2 DDATA2 Register Access No Bit Access Actionable Reads 866 25 6 35 CRYPTO_DDATA3 DDATA3 Register Access No Bit Access Actionable Reads 866 25 6 36 CRYPTO_DDATA4 DDATA4 Register Access No Bit Access Actionable Reads 867 25 6 37 CRYPTO_DDATA0BIG DDATA0 Register Big Endian Access No Bit Acce...

Page 952: ... Interrupt Port Select High Register 903 26 5 11 GPIO_EXTIPINSELL External Interrupt Pin Select Low Register 906 26 5 12 GPIO_EXTIPINSELH External Interrupt Pin Select High Register 909 26 5 13 GPIO_EXTIRISE External Interrupt Rising Edge Trigger Register 912 26 5 14 GPIO_EXTIFALL External Interrupt Falling Edge Trigger Register 912 26 5 15 GPIO_EXTILEVEL External Interrupt Level Register 913 26 5...

Page 953: ...or health which if it fails can be reasonably expected to result in significant personal injury or death Silicon Laboratories products are generally not intended for military applications Silicon Laboratories products shall under no circumstances be used in weapons of mass destruction including but not limited to nuclear biological or chemical weapons or missiles capable of delivering such weapons...

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