ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 108 -
Revision 2.4
System Control Register (SYSINFO_SCR)
Register
Offset
R/W Description
Reset Value
SYSINFO_SCR
SYS0x010
R/W System Control Register
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
7
6
5
4
3
2
1
0
Reserved
SEVNONPN
Reserved
SLPDEEP
SLPONEXC
Reserved
Bits
Description
[31:5]
Reserved
[4]
SEVNONPN
Send Event on Pending Bit
0 = only enabled interrupts or events can wake-up the processor, disabled interrupts
are excluded.
1 = enabled events and all interrupts, including disabled interrupts, can wake-up the
processor.
When enabled, interrupt transitions from Inactive to Pending are included in the list
of wakeup events for the WFE instruction.
When an event or interrupt enters pending state, the event signal wakes up the
processor from WFE. If the processor is not waiting for an event, the event is
registered and affects the next WFE.
The processor also wakes up on execution of an SEV instruction.
[2]
SLPDEEP
Controls Whether the Processor Uses Sleep or Deep Sleep As Its Low Power
Mode
0 = sleep.
1 = deep sleep.
The SLPDEEP flag is also used in conjunction with CLK_PWRCTL register to enter
deeper power-down states than purely core sleep states.
[1]
SLPONEXC
Sleep on Exception
When set to 1, the core can enter a sleep state on an exception return to Thread
mode. This is the mode and exception level entered at reset, the base level of
execution. Setting this bit to 1 enables an interrupt driven application to avoid
returning to an empty main application.
[0]
Reserved
