ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 122 -
Revision 2.4
Clock Source Select Control Register 0
（
CLK_CLKSEL0
）
Register
Offset
R/W
Description
Reset Value
CLK_CLKSEL0
0x10 R/W
Clock Source Select Control Register 0
0x0000_0038
7
6
5
4
3
2
1
0
HIRCFSEL
STCLKSEL
HCLKSEL
Table 5-41 Clock Source Select Register 0 (CLK_CLKSEL0, address 0x5000_0210
Bits
Description
[31:6]
Reserved
[7:6]
HIRCFSEL
High Frequency RC Oscilltor Frequency Select Register.
These bits are protected, to write to bits first perform the unlock sequence.
00 = Trim for 49.152MHz selected.
01 = Trim for 32.768MHz selected.
10 = Trim for reserved.
[5:3]
STCLKSEL
MCU Cortex_M0 SYST Clock Source Select
These bits are protected, to write to bits first perform the unlock sequence.
000 = clock source from LIRC.
001 = clock source from LXT.
010 = clock source from LIRC divided by 2.
011 = clock source from HIRC divided by 2.
1xx = clock source from HCLK÷2
(Default).
Note that to use STCLKSEL as source of SysTic timer the CLKSRC bit of
SYST_CSR must be set to 0.
[2:0]
HCLKSEL
HCLK Clock Source Select
Ensure that related clock sources (pre-select and new-select) are enabled before
updating register.
These bits are protected, to write to bits first perform the unlock sequence.
000 = clock source from HIRC. (deafult)
001 = clock source from LXT.
010 = clock source from LIRC.
011 = clock source from HXT.
Others = Reserved.
