ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
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Revision 2.4
5.7
PWM Generator and Capture Timer
5.7.1
Introduction
The I91200 has two PWM generators which can be configured as 4 independent PWM outputs,
PWM0CH0, PWM0CH1, PWM0CH2 and PWM0CH3, or as a complementary PWM pairs with
programmable dead-zone generator. Each PWM Generator has an 8-bit pre-scaler, a clock divider
providing 5 divided frequencies (1, 1/2, 1/4, 1/8, 1/16), two PWM Timers including two clock selectors,
two 16-bit PWM down-counters for PWM period control, two 16-bit comparators for PWM duty control
and one dead-zone generator. The PWM Generator provides PWM interrupt flags which are set by
hardware when the corresponding PWM period down counter reaches zero. Each PWM interrupt
source, with its corresponding enable bit, can generate a PWM interrupt request to the CPU. The PWM
generator can be configured in one-shot mode to produce only one PWM cycle signal or continuous
mode to output a periodic PWM waveform.
When PWM_CTL.DTEN01 is set, PWM0CH0 and PWM0CH1 perform complementary paired PWM
function; the paired PWM timing, period, duty and dead-time are determined by PWM0 timer and Dead-
zone generator0. Refer to Figure 5-25 PWM Generator Architecture Diagram for the architecture of
PWM Timers.
To prevent PWM driving glitches to an output pin, the 16-bit period down-counter and 16-bit comparator
are implemented with a double buffer. When user writes data to the counter/comparator registers, the
updated value will not be load into the 16-bit down-counter/comparator until the down-counter reaches
zero.
When the 16-bit period down-counter reaches zero, the interrupt request is generated. If PWM timer is
configured in continuous mode, when the down counter reaches zero, it is reloaded with PWM Counter
Register automatically and begins decrementing again. If the PWM timer is configured in one-shot
mode, the down counter will stop and generate a single interrupt request when it reaches zero.
The value of PWM counter comparator is used for pulse width modulation. The counter control logic
inverts the output level when down-counter value matches the value of compare register.
The alternate function of the PWM-timer is as a digital input capture timer. If Capture function is
enabled the PWM output pin is switched as a capture input pin. The Capture0 and PWM0CH0 share
one timer which is included in PWM0CH0; and the Capture1 and PWM0CH1 share PWM0CH1 timer.
User must setup the PWM-timer before enabling the Capture feature. After the capture feature is
enabled, the count is latched to the Capture Rising Latch Register (RCAPDAT) when input channel has
a rising transition and latched to Capture Falling Latch Register (PWM_FCAPDATx) when input
channel has a falling transition. Capture channel 0 interrupt is programmable by setting
PWM_CAPCTL01.CRLIEN0[1] (Rising latch Interrupt enable) and PWM_CAPCTL01.CFLIEN0[2]]
(Falling latch Interrupt enable) to determine the condition of interrupt occurrence. Capture channel 1
has the same feature by setting PWM_CAPCTL01.CRLIEN1[17] and PWM_CAPCTL01.CFLIEN1[18].
Whenever Capture issues interrupt, the PWM counter will also be reloaded.
5.7.2
Features
5.7.2.1
PWM function features:
PWM Generator, incorporating an 8-bit pre-scaler, clock divider, two PWM-timers (down
counters), a dead-zone generator and two PWM outputs.
Up to 4 PWM channels or two paired PWM channel.
16 bits resolution.
PWM Interrupt request synchronous with PWM period.
Single-shot or Continuous mode PWM.
Dead-Zone generator.
