ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
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Revision 2.4
5.9.4.3
Slave Select
In master mode, the SPI controller can address up to two off-chip slave devices through the slave
select output pins SPI0_SSB0 and SPI0_SSB1. Only one slave can be addressed at any one time. If
more slave address lines are required, GPIO pins can be manually configured to provide additional
SSB lines. In slave mode, the off-chip master device drives the slave select signal SPI0_SSB0 to
address the SPI controller. The slave select signal can be programmed to be active low or active high
via the SPI0_SSCTL.SSACTPOL bit. In addition the SPI0_SSCTL.SSLTRIG bit defines whether the
slave select signals are level triggered or edge triggered. The selection of trigger condition depends on
what type of peripheral slave/master device is connected.
5.9.4.4
Automatic Slave Select
In master mode, if the bit SPI0_SSCTL.ASS is set, the slave select signals will be generated
automatically and output to SPI0_SSB0 and SPI0_SSB1 pins according to registers
SPI0_SSCTL.SS[0] and SPI0_SSCTL.SS[1]. In this mode, SPI0 controller will assert SSB when
transaction is triggered and de-assert when data transfer is finished. If the SPI0_SSCTL.ASS bit is
cleared, the slave select output signals are asserted and de-asserted by manual setting and clearing
the related bits in the SPI0_SSCTL.SS[1:0] register. The active level of the slave select output signals
is specified by the SPI0_SSCTL.SSACTPOL bit.
In Master mode, if the value of SUSPITV[3:0] is less than 3 and AUTOSS is enabled, the slave select
signal will be kept in active state between two successive transactions.
In Slave mode, to recognize the inactive state of the slave select signal, the inactive period of the slave
select signal must be larger than or equal to 3 engine clock periods between two successive
transactions.
5.9.4.5
Serial Clock
In master mode, writing a divisor into the SPI0_CLKDIV.DIVIDER register will program the output
frequency of serial clock to the SPI0_SCLK output port. In slave mode, the off-chip master device
drives the serial clock through the SPI0_SCLK.
5.9.4.6
Clock Polarity
The SPI0_CTL.CLKPOL bit defines the serial clock idle state in master mode. If CLKPOL = 1, the
output SPI0_SCLK is high in idle state. If CLKPOL=0,it is low in idle state.
5.9.4.7
Transmit/Receive Bit Length
The bit length of a transfer word is defined in SPI0_CTL.DWIDTH bit field. It is set to define the length
of a transfer word and can be up to 32 bits in length. DWIDTH=0x0 enables 32bit word length.
5.9.4.8
LSB First
The SPI0_CTL.LSB bit defines the
bit
order of data transmission. If LSB=0 then MSB of transfer word
is sent first in time. If LSB=1 then LSB of transfer word is sent first in time. If REORDER is active, then
the LSB=1 causes the bit order of each byte to be reversed, not the bit order of the short or word
transmission.
For transmission, if DWIDTH is a byte multiple and LSB=1 , bytes are always reordered.
LSB is not valid and must be set to 0 for DUAL or QUAD SPI transactions.
5.9.4.9
Transmit Edge
The SPI0_CTL.TXNEG bit determines whether transmit data is changed on the positive or negative
edge of the SPI0_SCLK serial clock. If TXNEG=0 then transmitted data will change state on the rising
edge of SPI0_SCLK. If TXNEG=1 then transmitted data will change state on the falling edge of
SPI0_SCLK.
5.9.4.10
Receive Edge
The SPI0_CTL.RXNEG bit determines whether data is received at either the negative edge or positive
