ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 150 -
Revision 2.4
Detection Time Multiplex Register (BOD_BODDTMR)
The BOD detector can be set up to take periodic samples of the supply voltage to minimize power
consumption. The circuit can be configured and used in Standby Power Down (SPD) mode and can
wake up the device if a BOD is event detected. The detection timer uses the OSC10k oscillator as time
base so this oscillator must be active for timer operation. When active the BOD circuit requires ~165uA.
With default timer settings, average current reduces to 500nA
165uA*DURTON/(DURTOFF).
Register
Offset
R/W Description
Reset Value
BOD_BODDTMR
0x10
R/W Brown Out Detector Timer Register
0x0003_03E3
Table 5-61 Detection Time Multiplex
Register
(BOD_BODDTMR, address 0x4008_4010)
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
DURTON[3:0]
15
14
13
12
11
10
9
8
DURTOFF[15:8]
7
6
5
4
3
2
1
0
DURTOFF[7:0]
Bits
Description
[31:20]
Reserved
Reserved.
[19:16]
DURTON
Time BOD Detector Is Active
(1) * 100us. Minimum value is 1. (default is 400us)
[15:0]
DURTOFF
Time BOD Detector Is Off
(1)*100us . Minimum value is 7. (default is 99.6ms)
5.6
I2C Serial Interface Controller (Master/Slave)
5.6.1
Introduction
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange
between devices. The I2C standard is a true multi-master bus including collision detection and
arbitration that prevents data corruption if two or more masters attempt to control the bus
simultaneously. Serial, 8-bit oriented, bi-directional data transfers can be made up 1.0 Mbps.
Data is transferred between a Master and a Slave synchronously to SCL on the SDA line on a byte-by-
byte basis. Each data byte is 8 bits long. There is one SCL clock pulse for each data bit with the MSB
being transmitted first. An acknowledge bit follows each transferred byte. Each bit is sampled during the
high period of SCL; therefore, the SDA line may be changed only during the low period of SCL and
must be held stable during the high period of SCL. A transition on the SDA line while SCL is high is
interpreted as a command (START or STOP).
