ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
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Revision 2.4
5.2
System Manager
5.2.1
Overview
The following functions are included in system manager section
System Memory Map
System Timer (SysTick)
Nested Vectored Interrupt Controller (NVIC)
System management registers for product ID
System management registers for chip and module functional reset and multi-function pin control
Brown-Out and chip miscellaneous Control Register
Combined peripheral interrupt source identify
5.2.2
System Reset
The system reset includes one of the list below event occurs. For these reset event flags can be read
by
SYS_RSTSTS register.
The Power-On Reset
The low level on the RESETN pin
Watchdog Time Out Reset
Low Voltage Reset
Cortex-M0 MCU Reset
PMU Reset – for details of wakeup events, also examine CLK_PWRCTL register.
SWD Debug interface.
A power-on reset (POR) will occur if the main external supply rail ramps from 0V or the voltage of the
main supply drops below reset threshold. A low voltage reset monitors the regulated core logic (1.5V)
supply and will assert if the voltage on this rail drops below reliable logic threshold.
