ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 33 -
Revision 2.4
IP Reset Control Register1(SYS_IPRST0)
Register
Offset
R/W
Description
Reset Value
SYS_IPRST0
0x08
R/W
IP Reset Control Resister0
0x0000_0000
7
6
5
4
3
2
1
0
Reserved
PDMARST
CPURST
CHIPRST
Table 5-4 IP Reset Control Register 1 (SYS_IPRST0 address 0x5000_0008) Bit Description.
Bits
Description
[31:3]
Reserved
Reserved.
[2]
PDMARST
PDMA Controller Reset
Set “1” will generate a reset signal to the PDMA Block. User needs to set this bit to
“0” to release from the reset state
0= Normal operation.
1= PDMA IP reset.
[1]
CPURST
CPU Kernel One Shot Reset
Setting this bit will reset the CPU kernel and Flash Memory Controller(FMC), this bit
will automatically return to “0” after the 2 clock cycles
This bit is a protected bit, to program first issue the unlock sequence
0= Normal.
1= Reset CPU.
[0]
CHIPRST
CHIP One Shot Reset
Set this bit will reset the whole chip, this bit will automatically return to “0” after the 2
clock cycles.
CHIPRST has same behavior as POR reset, all the chip modules are reset and the
chip configuration settings from flash are reloaded.
This bit is a protected bit, to program first issue the unlock sequence
0= Normal.
1= Reset CHIP.
