ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 239 -
Revision 2.4
SPI Slave Select Register (SPI0_SSCTL)
Register
Offset
R/W
Description
Reset Value
SPI0_SSCTL
S 0x08 R/W
Slave Select Register
0x0000_0000
31
30
29
28
27
26
25
24
SLVTOCNT[15:8]
23
22
21
20
19
18
17
16
SLVTOCNT[7:0]
15
14
13
12
11
10
9
8
Reserved
SSINAIEN
SSACTIEN
Reserved
SLVUDRIEN
SLVBCEIEN
7
6
5
4
3
2
1
0
Reserved
SLVTORST
SLVTOIEN
SLV3WIRE
AUTOSS
SSACTPOL
SS
Table 5-93 SPI Slave Select Register (SPI0_SSCTL, address 0x4003_0008)
Bits
Description
[31:16]
SLVTOCNT
Slave Mode Time-out Period
In Slave mode, these bits indicate the time out period when there is serial clock input
during slave select active. The clock source of the time out counter is Slave engine clock.
If the value is 0, it indicates the slave mode time-out function is disabled.
[15:14]
Reserved
Reserved.
[13]
SSINAIEN
Slave Select Inactive Interrupt Enable
0 = Slave select inactive interrupt Disable.
1 = Slave select inactive interrupt Enable.
[12]
SSACTIEN
Slave Select Active Interrupt Enable
0 = Slave select active interrupt Disable.
1 = Slave select active interrupt Enable.
[11:10]
Reserved
Reserved.
[9]
SLVUDRIEN
Slave Mode Error 1 Interrupt Enable
0 = Slave mode error 1 interrupt Disable.
1 = Slave mode error 1 interrupt Enable.
[8]
SLVBCEIEN
Slave Mode Error 0 Interrupt Enable
0 = Slave mode error 0 interrupt Disable.
1 = Slave mode error 0 interrupt Enable.
[7]
Reserved
Reserved.
[6]
SLVTORST
Slave Mode Time-out FIFO Clear
0 = Function disabled.
1 = Both the FIFO clear function, TXRST and RXRST, are activated automatically when
there is a slave mode time-out event.
[5]
SLVTOIEN
Slave Mode Time-out Interrupt Enable
